diff options
| author | Christoph G. Baumann <c.baumann@ppc-ag.de> | 2013-10-28 12:29:31 +0100 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2013-10-31 17:54:23 +0100 |
| commit | 465ac5891c0302d33a59700711f3f0f1e81392fa (patch) | |
| tree | c047693a9974b64722eb83e031a15e1b6209f608 /board/imx31_phycore/Makefile | |
| parent | a0f97610757d6370fc58849032b36a94b4167fdc (diff) | |
ARM: mxs: Configure 2 Gbit DDR2 RAM for BG0900
The BG0900 module has 2Gbit DRAM module on it, adjust the DataBahn
DRAM controller registers so the DRAM module will be correctly
recognised.
Signed-off-by: Christoph G. Baumann <c.baumann@ppc-ag.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'board/imx31_phycore/Makefile')
0 files changed, 0 insertions, 0 deletions