diff options
| author | wdenk <wdenk> | 2003-03-06 13:39:27 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2003-03-06 13:39:27 +0000 |
| commit | 47cd00fa707af9de76408b69d3e911717dbbfab1 (patch) | |
| tree | dd887729a4eaf11e7a225563f4c604ef4b7d695b /board/innokom/memsetup.S | |
| parent | db2f721ffcf9693086a7e5c6c7015f2019e7f52e (diff) | |
* Patches by Robert Schwebel, 06 Mar 2003:
- fix bug in BOOTP code (must use NetCopyIP)
- update of CSB226 port
- clear BSS segment on XScale
- added support for i2c_init_board() function
- update to the Innokom plattform
* Extend support for redundand environments for configurations where
environment size < sector size
Diffstat (limited to 'board/innokom/memsetup.S')
| -rw-r--r-- | board/innokom/memsetup.S | 38 |
1 files changed, 25 insertions, 13 deletions
diff --git a/board/innokom/memsetup.S b/board/innokom/memsetup.S index f7d5eee575..a2bc99d12d 100644 --- a/board/innokom/memsetup.S +++ b/board/innokom/memsetup.S @@ -38,6 +38,9 @@ DRAM_SIZE: .long CFG_DRAM_SIZE sub pc,pc,#4 .endm +_TEXT_BASE: + .word TEXT_BASE + /* * Memory setup @@ -222,6 +225,12 @@ mem_init: /* Step 2c: Write FLYCNFG FIXME: what's that??? */ /* ---------------------------------------------------------------- */ + /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */ + adr r3, mem_init /* r0 <- current position of code */ + ldr r2, =mem_init + cmp r3, r2 /* skip init if in place */ + beq initirqs + /* ---------------------------------------------------------------- */ /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ @@ -313,17 +322,23 @@ mem_init: /* documented in SDRAM data sheets. The address(es) used */ /* for this purpose must not be cacheable. */ - ldr r3, =CFG_DRAM_BASE - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] + /* There should 9 writes, since the first write doesn't */ + /* trigger a refresh cycle on PXA250. See Intel PXA250 and */ + /* PXA210 Processors Specification Update, */ + /* Jan 2003, Errata #116, page 30. */ + ldr r3, =CFG_DRAM_BASE + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + /* Step 4g: Write MDCNFG with enable bits asserted */ /* (MDCNFG:DEx set to 1). */ @@ -339,7 +354,6 @@ mem_init: /* We are finished with Intel's memory controller initialisation */ - /* ---------------------------------------------------------------- */ /* Disable (mask) all interrupts at interrupt controller */ /* ---------------------------------------------------------------- */ @@ -405,8 +419,7 @@ initclks: /* FIXME */ -#define NODEBUG -#ifdef NODEBUG +#ifndef DEBUG /*Disable software and data breakpoints */ mov r0,#0 mcr p15,0,r0,c14,c8,0 /* ibcr0 */ @@ -416,7 +429,6 @@ initclks: /*Enable all debug functionality */ mov r0,#0x80000000 mcr p14,0,r0,c10,c0,0 /* dcsr */ - #endif /* ---------------------------------------------------------------- */ |