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authorBin Meng <bmeng.cn@gmail.com>2015-07-30 03:49:14 -0700
committerSimon Glass <sjg@chromium.org>2015-08-05 08:42:39 -0600
commit456ee909d63a35daa51b70231c4abffa4709e9f3 (patch)
tree28a7843c75ca798718a9b70906ac4b1250a4d297 /board/intel/minnowmax
parent1e7a04730426a96110989ed9c2bafb0d66ec2428 (diff)
x86: minnowmax: Remove smsc47x superio codes
On Intel BayTrail SoC, there is a legacy UART (I/O 0x3f8) integrated into the SoC which is enabled by the FSP. Remove the smsc47x superio initialization codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'board/intel/minnowmax')
-rw-r--r--board/intel/minnowmax/minnowmax.c12
1 files changed, 0 insertions, 12 deletions
diff --git a/board/intel/minnowmax/minnowmax.c b/board/intel/minnowmax/minnowmax.c
index 383cae068b..c4f2c33b87 100644
--- a/board/intel/minnowmax/minnowmax.c
+++ b/board/intel/minnowmax/minnowmax.c
@@ -6,12 +6,7 @@
#include <common.h>
#include <asm/gpio.h>
-#include <asm/ibmpc.h>
-#include <asm/pnp_def.h>
#include <netdev.h>
-#include <smsc_lpc47m.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, 4)
int arch_early_init_r(void)
{
@@ -21,13 +16,6 @@ int arch_early_init_r(void)
return 0;
}
-int board_early_init_f(void)
-{
- lpc47m_enable_serial(SERIAL_DEV, UART0_BASE, UART0_IRQ);
-
- return 0;
-}
-
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
{
return;