Merge branch 'arm/master' into arm/next

Conflicts:
	board/AtmarkTechno/suzaku/Makefile
	board/amcc/acadia/acadia.c
	board/amcc/katmai/katmai.c
	board/amcc/luan/luan.c
	board/amcc/ocotea/ocotea.c
	board/cm-bf537u/Makefile
	board/cray/L1/L1.c
	board/csb272/csb272.c
	board/csb472/csb472.c
	board/eric/eric.c
	board/eric/init.S
	board/eukrea/cpuat91/Makefile
	board/exbitgen/exbitgen.c
	board/exbitgen/init.S
	board/freescale/mpc8536ds/config.mk
	board/g2000/g2000.c
	board/jse/sdram.c
	board/mpl/mip405/mip405.c
	board/mpl/pip405/pip405.c
	board/netstal/hcu5/hcu5.c
	board/netstal/mcu25/mcu25.c
	board/sc3/sc3.c
	board/w7o/init.S
	board/w7o/w7o.c
	common/cmd_reginfo.c
	cpu/ppc4xx/40x_spd_sdram.c
	cpu/ppc4xx/44x_spd_ddr.c
	doc/README.sbc8548
	drivers/misc/fsl_law.c
	fs/ubifs/ubifs.c
	include/asm-ppc/immap_85xx.h

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>

2 files changed, 24 insertions, 24 deletions

diff --git a/board/jse/jse.c b/board/jse/jse.c
index 6dc9a01af8..1849ca47d7 100644
--- a/board/jse/jse.c
+++ b/board/jse/jse.c
@@ -48,12 +48,12 @@ int board_early_init_f (void)
    |       IRQ 30 (EXT IRQ 5) SystemACE BRdy (unused)
    |       IRQ 31 (EXT IRQ 6) (unused)
    +-------------------------------------------------------------------------*/
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr (uicer, 0x00000000);	/* disable all ints */
-	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical */
-	mtdcr (uicpr, 0xFFFFFF87);	/* set int polarities */
-	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
-	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr (UIC0PR, 0xFFFFFF87);	/* set int polarities */
+	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 
 	/* Configure the interface to the SystemACE MCU port.
 	   The SystemACE is fast, but there is no reason to have
diff --git a/board/jse/sdram.c b/board/jse/sdram.c
index bb6f85eee5..88fdd84130 100644
--- a/board/jse/sdram.c
+++ b/board/jse/sdram.c
@@ -35,59 +35,59 @@ phys_size_t initdram (int board_type)
 	/* Configure the SDRAMS */
 
 	/* disable memory controller */
-	mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
 	mtdcr (SDRAM0_CFGDATA, 0x00000000);
 
 	udelay (500);
 
 	/* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
-	mtdcr (SDRAM0_CFGADDR, mem_besra);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR0);
 	mtdcr (SDRAM0_CFGDATA, 0xffffffff);
 
 	/* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
-	mtdcr (SDRAM0_CFGADDR, mem_besrb);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR1);
 	mtdcr (SDRAM0_CFGDATA, 0xffffffff);
 
 	/* Clear SDRAM0_ECCCFG (disable ECC) */
-	mtdcr (SDRAM0_CFGADDR, mem_ecccf);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
 	mtdcr (SDRAM0_CFGDATA, 0x00000000);
 
 	/* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
-	mtdcr (SDRAM0_CFGADDR, mem_eccerr);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCESR);
 	mtdcr (SDRAM0_CFGDATA, 0xffffffff);
 
 	/* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */
-	mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
 	mtdcr (SDRAM0_CFGDATA, 0x010a4016);
 
 	/* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */
-	mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
 	mtdcr (SDRAM0_CFGDATA, 0x00084001);
 
 	/* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */
-	mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
 	mtdcr (SDRAM0_CFGDATA, 0x04084001);
 
 	/* Memory Bank 2 Config ==  BE=0 */
-	mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
 	mtdcr (SDRAM0_CFGDATA, 0x00000000);
 
 	/* Memory Bank 3 Config ==  BE=0 */
-	mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
 	mtdcr (SDRAM0_CFGDATA, 0x00000000);
 
 	/* refresh timer = 0x400  */
-	mtdcr (SDRAM0_CFGADDR, mem_rtr);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
 	mtdcr (SDRAM0_CFGDATA, 0x04000000);
 
 	/* Power management idle timer set to the default. */
-	mtdcr (SDRAM0_CFGADDR, mem_pmit);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_PMIT);
 	mtdcr (SDRAM0_CFGDATA, 0x07c00000);
 
 	udelay (500);
 
 	/* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */
-	mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
 	mtdcr (SDRAM0_CFGDATA, 0x80e00000);
 
 	return SDRAM_LEN;
@@ -108,7 +108,7 @@ int testdram (void)
 #ifdef DEBUG
 	printf ("SDRAM Controller Registers --\n");
 
-	mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
 	val = mfdcr (SDRAM0_CFGDATA);
 	printf ("    SDRAM0_CFG   : 0x%08x\n", val);
 
@@ -116,19 +116,19 @@ int testdram (void)
 	val = mfdcr (SDRAM0_CFGDATA);
 	printf ("    SDRAM0_STATUS: 0x%08x\n", val);
 
-	mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
 	val = mfdcr (SDRAM0_CFGDATA);
 	printf ("    SDRAM0_B0CR  : 0x%08x\n", val);
 
-	mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
 	val = mfdcr (SDRAM0_CFGDATA);
 	printf ("    SDRAM0_B1CR  : 0x%08x\n", val);
 
-	mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
 	val = mfdcr (SDRAM0_CFGDATA);
 	printf ("    SDRAM0_TR    : 0x%08x\n", val);
 
-	mtdcr (SDRAM0_CFGADDR, mem_rtr);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
 	val = mfdcr (SDRAM0_CFGDATA);
 	printf ("    SDRAM0_RTR   : 0x%08x\n", val);
 #endif