arm: imx53: Add support for imx53 boards from K+P

This commit adds support for DDC and HSC boards from
K+P in u-boot.

Console output:

U-Boot 2018.05-rc2-00090-g752b7ed6f9 (Apr 26 2018 - 14:24:24 +0200)

CPU:   Freescale i.MX53 rev2.1 at 800 MHz
Reset cause: WDOG
Model: K+P iMX53
DRAM:  512 MiB
MMC:   FSL_SDHC: 0
Loading Environment from MMC... OK
In:    serial
Out:   serial
Err:   serial
Module EEPROM:
  ID: TQMa53-CB.0401
  SN: 63152762
  MAC: 00:0b:64:03:14:2a
BBoard:40x0 Rev:10
Net:   eth0: ethernet@63fec000
Hit any key to stop autoboot:  0

Signed-off-by: Lukasz Majewski <lukma@denx.de>

1 files changed, 212 insertions, 0 deletions

diff --git a/board/k+p/kp_imx53/kp_imx53.c b/board/k+p/kp_imx53/kp_imx53.c
new file mode 100644
index 0000000000..7d2731208f
--- /dev/null
+++ b/board/k+p/kp_imx53/kp_imx53.c
@@ -0,0 +1,212 @@
+/*
+ * Copyright (C) 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/arch/clock.h>
+#include <asm/gpio.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include "kp_id_rev.h"
+
+#define VBUS_PWR_EN IMX_GPIO_NR(7, 8)
+#define PHY_nRST IMX_GPIO_NR(7, 6)
+#define BOOSTER_OFF IMX_GPIO_NR(2, 23)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	u32 size;
+
+	size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+	gd->ram_size = size;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+	struct fuse_bank *bank = &iim->bank[0];
+	struct fuse_bank0_regs *fuse =
+		(struct fuse_bank0_regs *)bank->fuse_regs;
+
+	int rev = readl(&fuse->gp[6]);
+
+	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
+
+#ifdef CONFIG_USB_EHCI_MX5
+int board_ehci_hcd_init(int port)
+{
+	gpio_request(VBUS_PWR_EN, "VBUS_PWR_EN");
+	gpio_direction_output(VBUS_PWR_EN, 1);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[] = {
+	{MMC_SDHC3_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1; /* eMMC is always present */
+}
+
+#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+				 PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+				 PAD_CTL_DSE_HIGH)
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+
+	static const iomux_v3_cfg_t sd3_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
+			     SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
+	};
+
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	imx_iomux_v3_setup_multiple_pads(sd3_pads, ARRAY_SIZE(sd3_pads));
+
+	ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+#endif
+
+static int power_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = pmic_get("mc34708", &dev);
+	if (ret) {
+		printf("%s: mc34708 not found !\n", __func__);
+		return ret;
+	}
+
+	/* Set VDDGP to 1.110V for 800 MHz on SW1 */
+	pmic_clrsetbits(dev, REG_SW_0, SWx_VOLT_MASK_MC34708,
+			SWx_1_110V_MC34708);
+
+	/* Set VCC as 1.30V on SW2 */
+	pmic_clrsetbits(dev, REG_SW_1, SWx_VOLT_MASK_MC34708,
+			SWx_1_300V_MC34708);
+
+	/* Set global reset timer to 4s */
+	pmic_clrsetbits(dev, REG_POWER_CTL2, TIMER_MASK_MC34708,
+			TIMER_4S_MC34708);
+
+	return ret;
+}
+
+static void setup_clocks(void)
+{
+	int ret;
+	u32 ref_clk = MXC_HCLK;
+	/*
+	 * CPU clock set to 800MHz and DDR to 400MHz
+	 */
+	ret = mxc_set_clock(ref_clk, 800, MXC_ARM_CLK);
+	if (ret)
+		printf("CPU:   Switch CPU clock to 800MHZ failed\n");
+
+	ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
+	ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
+	if (ret)
+		printf("CPU:   Switch DDR clock to 400MHz failed\n");
+}
+
+static void setup_ups(void)
+{
+	gpio_request(BOOSTER_OFF, "BOOSTER_OFF");
+	gpio_direction_output(BOOSTER_OFF, 0);
+}
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+void eth_phy_reset(void)
+{
+	gpio_request(PHY_nRST, "PHY_nRST");
+	gpio_direction_output(PHY_nRST, 1);
+	udelay(50);
+	gpio_set_value(PHY_nRST, 0);
+	udelay(400);
+	gpio_set_value(PHY_nRST, 1);
+	udelay(50);
+}
+
+int board_late_init(void)
+{
+	int ret = 0;
+
+	setup_ups();
+
+	if (!power_init())
+		setup_clocks();
+
+	ret = read_eeprom();
+	if (ret)
+		printf("Error %d reading EEPROM content!\n", ret);
+
+	eth_phy_reset();
+
+	show_eeprom();
+	read_board_id();
+
+	return ret;
+}