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authorYork Sun <yorksun@freescale.com>2012-02-29 12:36:51 +0000
committerAndy Fleming <afleming@freescale.com>2012-04-24 23:58:30 -0500
commit1ba62f10172ead798a8176435cfffff2f79f21c5 (patch)
tree5e9b575825060fae4ebefa3193ad5f1124c0fefd /board/karo/tx25
parent119a55f9cff4884a0ad3353d8752ee8787e232da (diff)
powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards
P1010RDB and p1_pc_rdb_pc has incorrect configuration for CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING. Incorrect setting causes DDR failure in case of SPD absent. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/karo/tx25')
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