diff options
| author | Gerlando Falauto <gerlando.falauto@keymile.com> | 2014-02-13 16:43:00 +0100 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-02-13 17:45:36 +0100 |
| commit | 9c134e189a95c976dab94d4f28444a5398627188 (patch) | |
| tree | f261253dd57b44c56705c5df2311fb7edbb013eb /board/keymile/km_arm/fpga_config.c | |
| parent | b1c2a7ae32b6c5dd1dcb7cb29c862af01523ba36 (diff) | |
arm/km: introduce kmsugp1 target
KMSUGP1 is from a u-boot perspective (almost) identical to KMNUSA.
The only difference is that the PCIe reset is connected to Kirkwood pin
MPP7_PEX_RST_OUTn, we use a dedicated config flag KM_PCIE_RESET_MPP7.
Such pin should theoretically be handled by the PCIe subsystem
automatically, but this turned out not to be the case.
So simply configure this PIN as a GPIO and issue a pulse manually.
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Cc: Karlheinz Jerg <karlheinz.jerg@keymile.com>
Cc: Valentin Longchamp <valenting.longchamp@keymile.com>
Cc: Holger Brunck <holger.brunck@keymile.com>
Acked-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Diffstat (limited to 'board/keymile/km_arm/fpga_config.c')
| -rw-r--r-- | board/keymile/km_arm/fpga_config.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c index cbfc7d2175..51a3cfe647 100644 --- a/board/keymile/km_arm/fpga_config.c +++ b/board/keymile/km_arm/fpga_config.c @@ -189,6 +189,31 @@ int wait_for_fpga_config(void) return 0; } +#if defined(KM_PCIE_RESET_MPP7) + +#define KM_PEX_RST_GPIO_PIN 7 +int fpga_reset(void) +{ + if (!check_boco2()) { + /* we do not have BOCO2, this is not really used */ + return 0; + } + + printf("PCIe reset through GPIO7: "); + /* apply PCIe reset via GPIO */ + kw_gpio_set_valid(KM_PEX_RST_GPIO_PIN, 1); + kw_gpio_direction_output(KM_PEX_RST_GPIO_PIN, 1); + kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 0); + udelay(1000*10); + kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 1); + + printf(" done\n"); + + return 0; +} + +#else + #define PRST1 0x4 #define PCIE_RST 0x10 #define TRAFFIC_RST 0x04 @@ -219,6 +244,7 @@ int fpga_reset(void) return 0; } +#endif /* the FPGA was configured, we configure the BOCO2 so that the EEPROM * is available from the Bobcat SPI bus */ |