powerpc/83xx/km: add MV88E6122 switch support for kmvect1

kmvect1 has a UEC2 connection to the piggy board and a UEC0 connection
to the switch MV88E6122. This switch has a connection to a frontport
ethernet interface. The ethernet port used for network booting is
automatically selected by u-boot. If a Piggy is plugged, the Piggy
port is selected (UEC2, eth1). If the Piggy isn't present, the
Frontport is selected (UEC0, eth0).

The switch reset is connected to a GPIO on the PRIO3 board FPGA (GPIO28)
and released at startup.

Signed-off-by: Karlheinz Jerg <karlheinz.jerg@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>

2 files changed, 74 insertions, 1 deletions

diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c
index d568fd9def..22d525602a 100644
--- a/board/keymile/common/ivm.c
+++ b/board/keymile/common/ivm.c
@@ -233,7 +233,13 @@ static int ivm_analyze_block2(unsigned char *buf, int len)
 	if (getenv("ethaddr") == NULL)
 		setenv((char *)"ethaddr", (char *)valbuf);
 #endif
-
+#ifdef CONFIG_KMVECT1
+/* KMVECT1 has two ethernet interfaces */
+	if (getenv("eth1addr") == NULL) {
+		calculate_mac_offset(buf, valbuf, 1);
+		setenv((char *)"eth1addr", (char *)valbuf);
+	}
+#endif
 	/* IVM_MacCount */
 	count = (buf[10] << 24) +
 		   (buf[11] << 16) +
diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c
index b027173725..1e8e2cc360 100644
--- a/board/keymile/km83xx/km83xx.c
+++ b/board/keymile/km83xx/km83xx.c
@@ -215,8 +215,75 @@ int misc_init_r(void)
 	return 0;
 }
 
+#if defined(CONFIG_KMVECT1)
+#include <mv88e6352.h>
+/* Marvell MV88E6122 switch configuration */
+static struct mv88e_sw_reg extsw_conf[] = {
+	/* port 1, FRONT_MDI, autoneg */
+	{ PORT(1), PORT_PHY, NO_SPEED_FOR },
+	{ PORT(1), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+	{ PHY(1), PHY_1000_CTRL, NO_ADV },
+	{ PHY(1), PHY_SPEC_CTRL, AUTO_MDIX_EN },
+	{ PHY(1), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
+		FULL_DUPLEX },
+	/* port 2, unused */
+	{ PORT(2), PORT_CTRL, PORT_DIS },
+	{ PHY(2), PHY_CTRL, PHY_PWR_DOWN },
+	{ PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+	/* port 3, BP_MII (CPU), PHY mode, 100BASE */
+	{ PORT(3), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+	/* port 4, ESTAR to slot 11, SerDes, 1000BASE-X */
+	{ PORT(4), PORT_STATUS, NO_PHY_DETECT },
+	{ PORT(4), PORT_PHY, SPEED_1000_FOR },
+	{ PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+	/* port 5, ESTAR to slot 13, SerDes, 1000BASE-X */
+	{ PORT(5), PORT_STATUS, NO_PHY_DETECT },
+	{ PORT(5), PORT_PHY, SPEED_1000_FOR },
+	{ PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+	/*
+	 * Errata Fix: 1.9V Output from Internal 1.8V Regulator,
+	 * acc . MV-S300889-00D.pdf , clause 4.5
+	 */
+	{ PORT(5), 0x1A, 0xADB1 },
+	/* port 6, unused, this port has no phy */
+	{ PORT(6), PORT_CTRL, PORT_DIS },
+};
+#endif
+
 int last_stage_init(void)
 {
+#if defined(CONFIG_KMVECT1)
+	struct km_bec_fpga __iomem *base =
+		(struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
+	u8 tmp_reg;
+
+	/* Release mv88e6122 from reset */
+	tmp_reg = in_8(&base->res1[0]) | 0x10; /* DIRECT3 register */
+	out_8(&base->res1[0], tmp_reg);	       /* GP28 as output */
+	tmp_reg = in_8(&base->gprt3) | 0x10;   /* GP28 to high */
+	out_8(&base->gprt3, tmp_reg);
+
+	/* configure MV88E6122 switch */
+	char *name = "UEC2";
+
+	if (miiphy_set_current_dev(name))
+		return 0;
+
+	mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
+		ARRAY_SIZE(extsw_conf));
+
+	mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
+
+	if (piggy_present()) {
+		setenv("ethact", "UEC2");
+		setenv("netdev", "eth1");
+		puts("using PIGGY for network boot\n");
+	} else {
+		setenv("netdev", "eth0");
+		puts("using frontport for network boot\n");
+	}
+#endif
+
 #if defined(CONFIG_KMCOGE5NE)
 	struct bfticu_iomap *base =
 		(struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;