diff options
| author | Lukasz Majewski <lukma@denx.de> | 2018-05-11 16:51:13 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2018-06-18 15:44:21 +0200 |
| commit | ea4584d73d731c49cc838cae3955a2ef92d5eff7 (patch) | |
| tree | 3ada8bcf9f76f14d687d2d9a360e49901367defb /board/liebherr/display5/spl.c | |
| parent | b5f4543c92dd7be011b9729ee9c998c0e805c23e (diff) | |
display5: ddr: Enable support for DDR3 auto calibration
This code performs DDR3 memory calibration for display5 board.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Diffstat (limited to 'board/liebherr/display5/spl.c')
| -rw-r--r-- | board/liebherr/display5/spl.c | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/board/liebherr/display5/spl.c b/board/liebherr/display5/spl.c index 5c6b8bff38..0c0172e201 100644 --- a/board/liebherr/display5/spl.c +++ b/board/liebherr/display5/spl.c @@ -117,6 +117,49 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } +#ifdef CONFIG_MX6_DDRCAL +static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo) +{ + struct mx6_mmdc_calibration calibration = {0}; + + mmdc_read_calibration(sysinfo, &calibration); + + debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0); + debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1); + debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl); + debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl); + debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0); + debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1); + debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0); + debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1); + debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl); + debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl); + debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0); + debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1); +} + +static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo) +{ + int ret; + + /* Perform DDR DRAM calibration */ + udelay(100); + ret = mmdc_do_write_level_calibration(sysinfo); + if (ret) { + printf("DDR: Write level calibration error [%d]\n", ret); + return; + } + + ret = mmdc_do_dqs_calibration(sysinfo); + if (ret) { + printf("DDR: DQS calibration error [%d]\n", ret); + return; + } + + spl_dram_print_cal(sysinfo); +} +#endif /* CONFIG_MX6_DDRCAL */ + static void spl_dram_init(void) { struct mx6_ddr_sysinfo sysinfo = { @@ -143,6 +186,10 @@ static void spl_dram_init(void) mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125); + +#ifdef CONFIG_MX6_DDRCAL + spl_dram_perform_cal(&sysinfo); +#endif } #ifdef CONFIG_SPL_SPI_SUPPORT |