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authorNikita Kiryanov <nikita@compulab.co.il>2014-11-11 15:46:05 +0200
committerTom Rini <trini@ti.com>2014-11-12 13:02:22 -0500
commitecfdcee5d9299624c57f0118b137d06d376c115a (patch)
treeadf81fc6f95c3d967b242d1ffd6cd03935b14da3 /board/mcc200/mt48lc8m32b2-6-7.h
parentc88eaea0a0a809884388c3a5727d960bac0b0ced (diff)
powerpc: remove orphaned boards mcc200 and prs200
mcc200 and prs200 are old and have no maintainer. Remove the boards. This also removes the mcc200 specific 1bpp BMP support from common/lcd.c Cc: Wolfgang Denk <wd@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: York Sun <yorksun@freescale.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Diffstat (limited to 'board/mcc200/mt48lc8m32b2-6-7.h')
-rw-r--r--board/mcc200/mt48lc8m32b2-6-7.h12
1 files changed, 0 insertions, 12 deletions
diff --git a/board/mcc200/mt48lc8m32b2-6-7.h b/board/mcc200/mt48lc8m32b2-6-7.h
deleted file mode 100644
index 13aebbd8af..0000000000
--- a/board/mcc200/mt48lc8m32b2-6-7.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform
- */
-
-#define SDRAM_DDR 0 /* is SDR */
-
-/* Settings for XLB = 132 MHz */
-
-#define SDRAM_MODE 0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */
-#define SDRAM_CONTROL 0x504f0000 /* Control Register MBAR + 0x0104 */
-#define SDRAM_CONFIG1 0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */
-#define SDRAM_CONFIG2 0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */