diff options
| author | roy zang <tie-fei.zang@freescale.com> | 2006-12-04 23:57:35 +0800 |
|---|---|---|
| committer | Zang Tiefei <roy@bus.ap.freescale.net> | 2006-12-04 23:57:35 +0800 |
| commit | d3bb5ec198edad4869ac5276a5899881b7bf5433 (patch) | |
| tree | 409a70e937d5f826df7929d11cb08a7cd207f5cd /board/mcc200 | |
| parent | 41862d13a87ec58c21166b10fcb754c963bc46f2 (diff) | |
| parent | 9d27b3a0685ff99fc477983f315c04d49f657a8a (diff) | |
Merge /home/roy/CVS/7448/Open_Source/u-boot.git.dev
Diffstat (limited to 'board/mcc200')
| -rw-r--r-- | board/mcc200/mcc200.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c index 71a691b5db..5d74bdeb42 100644 --- a/board/mcc200/mcc200.c +++ b/board/mcc200/mcc200.c @@ -27,6 +27,7 @@ #include <common.h> #include <mpc5xxx.h> #include <pci.h> +#include <asm/processor.h> /* Two MT48LC8M32B2 for 32 MB */ /* #include "mt48lc8m32b2-6-7.h" */ @@ -98,6 +99,7 @@ long int initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; + uint svr, pvr; #ifndef CFG_RAMBOOT ulong test1, test2; @@ -192,6 +194,22 @@ long int initdram (int board_type) #endif /* CFG_RAMBOOT */ + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + } + return dramsize + dramsize2; } |