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| author | Icenowy Zheng <icenowy@aosc.xyz> | 2017-06-03 17:10:18 +0800 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2017-06-08 22:37:55 +0530 |
| commit | f6457ce5789b885706a2877edb70b5f8e61cf075 (patch) | |
| tree | 07a6c460c9a922c90ebf00a0522e3845970d4fbc /board/micronas/vct/vcth/reg_fwsram.h | |
| parent | 66b12526f0bdfb284a5152cd31d5eed849e7b873 (diff) | |
sunxi: Add selective DRAM type and timing
DRAM chip varies, and one code cannot satisfy all DRAMs.
Add options to select a timing set.
Currently only DDR3-1333 (the original set) is added into it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'board/micronas/vct/vcth/reg_fwsram.h')
0 files changed, 0 insertions, 0 deletions