diff options
| author | Dave Liu <daveliu@freescale.com> | 2006-11-03 12:11:15 -0600 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2006-11-03 19:42:21 -0600 |
| commit | 7737d5c658c606f999dfbe3e86b0fed49e5c50ef (patch) | |
| tree | d1bf347ba7f4292def53870ecfcba0a1dd4c6231 /board/mpc8360emds/mpc8360emds.c | |
| parent | 5f8204394e39bbe8cd9f08b8f8d145b6c01f7c73 (diff) | |
mpc83xx: add QE ethernet support
this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
Diffstat (limited to 'board/mpc8360emds/mpc8360emds.c')
| -rw-r--r-- | board/mpc8360emds/mpc8360emds.c | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index d70a4c3cbd..5eadcd39eb 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -29,6 +29,62 @@ #include <asm/mmu.h> #endif +const qe_iop_conf_t qe_iop_conf_tab[] = { + /* GETH1 */ + {0, 3, 1, 0, 1}, /* TxD0 */ + {0, 4, 1, 0, 1}, /* TxD1 */ + {0, 5, 1, 0, 1}, /* TxD2 */ + {0, 6, 1, 0, 1}, /* TxD3 */ + {1, 6, 1, 0, 3}, /* TxD4 */ + {1, 7, 1, 0, 1}, /* TxD5 */ + {1, 9, 1, 0, 2}, /* TxD6 */ + {1, 10, 1, 0, 2}, /* TxD7 */ + {0, 9, 2, 0, 1}, /* RxD0 */ + {0, 10, 2, 0, 1}, /* RxD1 */ + {0, 11, 2, 0, 1}, /* RxD2 */ + {0, 12, 2, 0, 1}, /* RxD3 */ + {0, 13, 2, 0, 1}, /* RxD4 */ + {1, 1, 2, 0, 2}, /* RxD5 */ + {1, 0, 2, 0, 2}, /* RxD6 */ + {1, 4, 2, 0, 2}, /* RxD7 */ + {0, 7, 1, 0, 1}, /* TX_EN */ + {0, 8, 1, 0, 1}, /* TX_ER */ + {0, 15, 2, 0, 1}, /* RX_DV */ + {0, 16, 2, 0, 1}, /* RX_ER */ + {0, 0, 2, 0, 1}, /* RX_CLK */ + {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */ + {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */ + /* GETH2 */ + {0, 17, 1, 0, 1}, /* TxD0 */ + {0, 18, 1, 0, 1}, /* TxD1 */ + {0, 19, 1, 0, 1}, /* TxD2 */ + {0, 20, 1, 0, 1}, /* TxD3 */ + {1, 2, 1, 0, 1}, /* TxD4 */ + {1, 3, 1, 0, 2}, /* TxD5 */ + {1, 5, 1, 0, 3}, /* TxD6 */ + {1, 8, 1, 0, 3}, /* TxD7 */ + {0, 23, 2, 0, 1}, /* RxD0 */ + {0, 24, 2, 0, 1}, /* RxD1 */ + {0, 25, 2, 0, 1}, /* RxD2 */ + {0, 26, 2, 0, 1}, /* RxD3 */ + {0, 27, 2, 0, 1}, /* RxD4 */ + {1, 12, 2, 0, 2}, /* RxD5 */ + {1, 13, 2, 0, 3}, /* RxD6 */ + {1, 11, 2, 0, 2}, /* RxD7 */ + {0, 21, 1, 0, 1}, /* TX_EN */ + {0, 22, 1, 0, 1}, /* TX_ER */ + {0, 29, 2, 0, 1}, /* RX_DV */ + {0, 30, 2, 0, 1}, /* RX_ER */ + {0, 31, 2, 0, 1}, /* RX_CLK */ + {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */ + {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */ + + {0, 1, 3, 0, 2}, /* MDIO */ + {0, 2, 1, 0, 1}, /* MDC */ + + {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ +}; + int board_early_init_f(void) { volatile u8 *bcsr = (volatile u8 *)CFG_BCSR; |