diff options
| author | Xie Xiaobo <r63061@freescale.com> | 2007-02-14 18:27:17 +0800 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2007-03-02 11:05:54 -0600 |
| commit | d61853cf2472e0b8bcbd131461a93d1c49ff0c1f (patch) | |
| tree | 993c4b0fda27f49928163533fddd09c26da97840 /board/mpc8360emds/mpc8360emds.c | |
| parent | b110f40bd180c6b560276589beedf753e97c46ce (diff) | |
mpc83xx: Add DDR2 controller fixed/SPD Init for MPC83xx
The code supply fixed and SPD initialization for MPC83xx DDR2 Controller.
it pass DDR/DDR2 compliance tests.
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Diffstat (limited to 'board/mpc8360emds/mpc8360emds.c')
| -rw-r--r-- | board/mpc8360emds/mpc8360emds.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index ddc1047c61..54b9acc6e9 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -158,6 +158,20 @@ int fixed_sdram(void) #if (CFG_DDR_SIZE != 256) #warning Currenly any ddr size other than 256 is not supported #endif +#ifdef CONFIG_DDR_II + im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; + im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; + im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_mode2 = CFG_DDR_MODE2; + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; +#else im->ddr.csbnds[0].csbnds = 0x00000007; im->ddr.csbnds[1].csbnds = 0x0008000f; @@ -170,6 +184,7 @@ int fixed_sdram(void) im->ddr.sdram_mode = CFG_DDR_MODE; im->ddr.sdram_interval = CFG_DDR_INTERVAL; +#endif udelay(200); im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; |