diff options
| author | Stefan Roese <sr@denx.de> | 2011-11-15 08:03:39 +0000 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2011-11-16 21:17:58 +0100 |
| commit | 4233fafe9e190fa57db6ca913978b02789bc98f7 (patch) | |
| tree | 1b89f3f901eaf272920519bafa65b781addf37ee /board/mpl/mip405 | |
| parent | 80b68f70fd528ec8292847dc634f16eb65b45de3 (diff) | |
mip405.c: Fix GCC 4.6 build warnings
Fix:
mip405.c: In function 'init_sdram':
mip405.c:250:4: warning: variable 'tctp_clocks' set but not used [-Wunused-but-set-variable]
mip405.c: In function 'initdram':
mip405.c:629:9: warning: variable 'ds' set but not used [-Wunused-but-set-variable]
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/mpl/mip405')
| -rw-r--r-- | board/mpl/mip405/mip405.c | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c index e93d99407c..9d0db64462 100644 --- a/board/mpl/mip405/mip405.c +++ b/board/mpl/mip405/mip405.c @@ -246,8 +246,7 @@ int init_sdram (void) unsigned char trp_clocks, trcd_clocks, tras_clocks, - trc_clocks, - tctp_clocks; + trc_clocks; unsigned char cal_val; unsigned char bc; unsigned long sdram_tim, sdram_bank; @@ -345,7 +344,6 @@ int init_sdram (void) trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */ tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */ /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */ - tctp_clocks = sdram_table[i].tctp; /* 44 - 20ns = 24ns */ /* trc_clocks is sum of trp_clocks + tras_clocks */ trc_clocks = trp_clocks + tras_clocks; /* get SDRAM timing register */ @@ -626,10 +624,9 @@ phys_size_t initdram (int board_type) { unsigned long bank_reg[4], tmp, bank_size; - int i, ds; + int i; unsigned long TotalSize; - ds = 0; /* since the DRAM controller is allready set up, calculate the size with the bank registers */ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); @@ -646,8 +643,7 @@ phys_size_t initdram (int board_type) tmp = (bank_reg[i] >> 17) & 0x7; bank_size = 4 << tmp; TotalSize += bank_size; - } else - ds = 1; + } } mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); tmp = mfdcr (SDRAM0_CFGDATA); |