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authorTom Rini <trini@konsulko.com>2019-01-17 19:12:55 -0500
committerTom Rini <trini@konsulko.com>2019-01-17 19:12:55 -0500
commitf83ef0dac83110d20389eb71f09285f009f3d198 (patch)
treee653de97fa1b8873704bd3d8afa557464c67e73c /board/mscc/common/spi.c
parente964df1e2ae7b2c041a9d767f03ad2b72a3f2ac7 (diff)
parent49f0b6bab919e6a9a509af841b43bbb49728dc45 (diff)
Merge tag 'mips-pull-2019-11-16' of git://git.denx.de/u-boot-mips
- MIPS: mscc: various enhancements for Luton and Ocelot platforms - MIPS: mscc: added support for Jaguar2 platform - MIPS: optimised SPL linker script - MIPS: bcm6368: fix restart flow issues - MIPS: fixed CONFIG_OF_EMBED warnings for all MIPS boards - MIPS: mt7688: small fixes and enhancements - mmc: compile-out write support if disabled
Diffstat (limited to 'board/mscc/common/spi.c')
-rw-r--r--board/mscc/common/spi.c31
1 files changed, 31 insertions, 0 deletions
diff --git a/board/mscc/common/spi.c b/board/mscc/common/spi.c
new file mode 100644
index 0000000000..0566fcba5c
--- /dev/null
+++ b/board/mscc/common/spi.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Coprporation
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <spi.h>
+
+void external_cs_manage(struct udevice *dev, bool enable)
+{
+ u32 cs = spi_chip_select(dev);
+ /* IF_SI0_OWNER, select the owner of the SI interface
+ * Encoding: 0: SI Slave
+ * 1: SI Boot Master
+ * 2: SI Master Controller
+ */
+ if (!enable) {
+ writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE |
+ ICPU_SW_MODE_SW_SPI_CS(BIT(cs)),
+ BASE_CFG + ICPU_SW_MODE);
+ clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
+ ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
+ ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
+ } else {
+ writel(0, BASE_CFG + ICPU_SW_MODE);
+ clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
+ ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
+ ICPU_GENERAL_CTRL_IF_SI_OWNER(1));
+ }
+}