diff options
| author | Horatiu Vultur <horatiu.vultur@microchip.com> | 2019-01-12 18:57:00 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2019-01-16 13:56:43 +0100 |
| commit | c75c908316983eb729ce7e6449959dcabd58413b (patch) | |
| tree | 01ddf059529697cc4c71f9e370addb3d1bb218c1 /board/mscc/ocelot/ocelot.c | |
| parent | 393b77d8f9c2d6da8cda99470aa484595a4d6096 (diff) | |
MSCC: Add board support for Jaguar2 SOC family
Add board support and configuration for Jaguar2 SOC family.
The detection of the board type in this family is based on the phy ids.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Diffstat (limited to 'board/mscc/ocelot/ocelot.c')
| -rw-r--r-- | board/mscc/ocelot/ocelot.c | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c index a05c308669..0f7a532158 100644 --- a/board/mscc/ocelot/ocelot.c +++ b/board/mscc/ocelot/ocelot.c @@ -18,28 +18,6 @@ enum { BOARD_TYPE_PCB123, }; -void external_cs_manage(struct udevice *dev, bool enable) -{ - u32 cs = spi_chip_select(dev); - /* IF_SI0_OWNER, select the owner of the SI interface - * Encoding: 0: SI Slave - * 1: SI Boot Master - * 2: SI Master Controller - */ - if (!enable) { - writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE | - ICPU_SW_MODE_SW_SPI_CS(BIT(cs)), BASE_CFG + ICPU_SW_MODE); - clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, - ICPU_GENERAL_CTRL_IF_SI_OWNER_M, - ICPU_GENERAL_CTRL_IF_SI_OWNER(2)); - } else { - writel(0, BASE_CFG + ICPU_SW_MODE); - clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, - ICPU_GENERAL_CTRL_IF_SI_OWNER_M, - ICPU_GENERAL_CTRL_IF_SI_OWNER(1)); - } -} - void board_debug_uart_init(void) { /* too early for the pinctrl driver, so configure the UART pins here */ |