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authorTom Warren <twarren.nvidia@gmail.com>2013-02-21 12:31:29 +0000
committerTom Warren <twarren@nvidia.com>2013-03-14 11:06:42 -0700
commit126685ad44ad39895567884458b3a4581acf8902 (patch)
treef4d2dd7e7cd1fffa7e4a91463768b2ec0f06498d /board/nvidia/dts/tegra20-seaboard.dts
parent90b079c8f989c0e949e2a275e77434aa4e16b8e0 (diff)
Tegra: fdt: Add/enhance sdhci (mmc) nodes for all T20 DT files
Linux dts files were used for those boards that didn't already have sdhci info populated. Tamonten has their own dtsi file with common sdhci nodes (sourced from Linux). Signed-off-by: Tom Warren <twarren@nvidia.com> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Reviewed-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'board/nvidia/dts/tegra20-seaboard.dts')
-rw-r--r--board/nvidia/dts/tegra20-seaboard.dts12
1 files changed, 8 insertions, 4 deletions
diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts
index a73db36f1e..12cb0bc780 100644
--- a/board/nvidia/dts/tegra20-seaboard.dts
+++ b/board/nvidia/dts/tegra20-seaboard.dts
@@ -12,14 +12,15 @@
};
aliases {
- /* This defines the order of our USB ports */
+ /* This defines the order of our ports */
usb0 = "/usb@c5008000";
usb1 = "/usb@c5000000";
-
i2c0 = "/i2c@7000d000";
i2c1 = "/i2c@7000c000";
i2c2 = "/i2c@7000c400";
i2c3 = "/i2c@7000c500";
+ sdhci0 = "/sdhci@c8000600";
+ sdhci1 = "/sdhci@c8000400";
};
memory {
@@ -156,13 +157,16 @@
};
sdhci@c8000400 {
- cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+ status = "okay";
+ cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 70 0>; /* gpio PI6 */
+ bus-width = <4>;
};
sdhci@c8000600 {
- support-8bit;
+ status = "okay";
+ bus-width = <8>;
};
lcd_panel: panel {