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authorTom Rini <trini@konsulko.com>2018-07-11 09:05:25 -0400
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2018-08-08 13:34:27 +0200
commit481ea2e39dacf227bc5d8a244352d03dfb9c0ac9 (patch)
treed2ba42cb8761220a4af001861232e33bb1e382fa /board/pb1x00
parent215b4fae518a1ddcd36817cd1e420fa03d058d8e (diff)
mips: au1x00: Remove support for these SoCs
The only platform left for the AU1x00 SoCs was the pb1x00 platform, an apparent clone of the dbau1x00 platform. As pb1x00 had no listed maintainer I am assuming that it is also orphaned. Remove this platform and then remove the unused SoC support. Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'board/pb1x00')
-rw-r--r--board/pb1x00/Kconfig27
-rw-r--r--board/pb1x00/MAINTAINERS6
-rw-r--r--board/pb1x00/Makefile7
-rw-r--r--board/pb1x00/README63
-rw-r--r--board/pb1x00/flash.c26
-rw-r--r--board/pb1x00/lowlevel_init.S391
-rw-r--r--board/pb1x00/pb1x00.c108
7 files changed, 0 insertions, 628 deletions
diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig
deleted file mode 100644
index ef8905d46a..0000000000
--- a/board/pb1x00/Kconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-if TARGET_PB1X00
-
-config SYS_BOARD
- default "pb1x00"
-
-config SYS_SOC
- default "au1x00"
-
-config SYS_CONFIG_NAME
- default "pb1x00"
-
-config SYS_TEXT_BASE
- default 0x83800000
-
-config SYS_DCACHE_SIZE
- default 16384
-
-config SYS_DCACHE_LINE_SIZE
- default 32
-
-config SYS_ICACHE_SIZE
- default 16384
-
-config SYS_ICACHE_LINE_SIZE
- default 32
-
-endif
diff --git a/board/pb1x00/MAINTAINERS b/board/pb1x00/MAINTAINERS
deleted file mode 100644
index 8326cc78cc..0000000000
--- a/board/pb1x00/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PB1X00 BOARD
-#M: -
-S: Maintained
-F: board/pb1x00/
-F: include/configs/pb1x00.h
-F: configs/pb1000_defconfig
diff --git a/board/pb1x00/Makefile b/board/pb1x00/Makefile
deleted file mode 100644
index 5ef9b7f43b..0000000000
--- a/board/pb1x00/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y = pb1x00.o flash.o
-obj-y += lowlevel_init.o
diff --git a/board/pb1x00/README b/board/pb1x00/README
deleted file mode 100644
index b1e9494118..0000000000
--- a/board/pb1x00/README
+++ /dev/null
@@ -1,63 +0,0 @@
-By Thomas.Lange@corelatus.se 2004-Oct-05
-----------------------------------------
-DbAu1xx0 are development boards from AMD containing
-an Alchemy AU1xx0 series cpu with mips32 core.
-Existing cpu:s are Au1000, Au1100, Au1500 and Au1550
-
-Limitations & comments
-----------------------
-Support was originally big endian only.
-I have not tested, but several u-boot users report working
-configurations in little endian mode.
-
-I named the board dbau1x00, to allow
-support for all three development boards
-( dbau1000, dbau1100 and dbau1500 ).
-Now there is a new board called dbau1550 also, which
-should be supported RSN.
-
-I only have a dbau1000, so my testing is limited
-to this board.
-
-The board has two different flash banks, that can
-be selected via dip switch. This makes it possible
-to test new bootloaders without thrashing the YAMON
-boot loader delivered with board.
-
-NOTE! When you switch between the two boot flashes, the
-base addresses will be swapped.
-Have this in mind when you compile u-boot. CONFIG_SYS_TEXT_BASE has
-to match the address where u-boot is located when you
-actually launch.
-
-Ethernet only supported for mac0.
-
-PCMCIA only supported for slot 0, only 3.3V.
-
-PCMCIA IDE tested with Sandisk Compact Flash and
-IBM microdrive.
-
-###################################
-######## NOTE!!!!!! #########
-###################################
-If you partition a disk on another system (e.g. laptop),
-all bytes will be swapped on 16bit level when using
-PCMCIA and running cpu in big endian mode!!!!
-
-This is probably due to an error in Au1000 chip.
-
-Solution:
-
-a) Boot via network and partition disk directly from
-dbau1x00. The endian will then be correct.
-
-b) Partition disk on "laptop" and fill it with all files
-you need. Then write a simple program that endian swaps
-whole disk,
-
-Example:
-Original "laptop" byte order:
-B0 B1 B2 B3 B4 B5 B6 B7 B8 B9...
-
-Dbau1000 byte order will then be:
-B1 B0 B3 B2 B5 B4 B7 B6 B9 B8...
diff --git a/board/pb1x00/flash.c b/board/pb1x00/flash.c
deleted file mode 100644
index c7daf5a0ef..0000000000
--- a/board/pb1x00/flash.c
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init (void)
-{
- printf ("Skipping flash_init\n");
- return (0);
-}
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- printf ("write_buff not implemented\n");
- return (-1);
-}
diff --git a/board/pb1x00/lowlevel_init.S b/board/pb1x00/lowlevel_init.S
deleted file mode 100644
index 98d9536a7d..0000000000
--- a/board/pb1x00/lowlevel_init.S
+++ /dev/null
@@ -1,391 +0,0 @@
-/* Memory sub-system initialization code */
-
-#include <config.h>
-#include <mach/au1x00.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-
-#define AU1500_SYS_ADDR 0xB1900000
-#define sys_endian 0x0038
-#define CP0_Config0 $16
-#define MEM_1MS ((396000000/1000000) * 1000)
-
- .text
- .set noreorder
- .set mips32
-
- .globl lowlevel_init
-lowlevel_init:
- /*
- * Step 1) Establish CPU endian mode.
- * NOTE: A fair amount of code is necessary on the Pb1000 to
- * obtain the value of Switch S8.1 which is used to determine
- * endian at run-time.
- */
-
- /* RCE1 */
- li t0, MEM_STCFG1
- li t1, 0x00000083
- sw t1, 0(t0)
-
- li t0, MEM_STTIME1
- li t1, 0x33030A10
- sw t1, 0(t0)
-
- li t0, MEM_STADDR1
- li t1, 0x11803E40
- sw t1, 0(t0)
-
- /* Set DSTRB bits so switch will read correctly */
- li t1, 0xBE00000C
- lw t2, 0(t1)
- or t2, t2, 0x00000300
- sw t2, 0(t1)
-
- /* Check switch setting */
- li t1, 0xBE000014
- lw t2, 0(t1)
- and t2, t2, 0x00000100
- bne t2, zero, big_endian
- nop
-
-little_endian:
-
- /* Change Au1 core to little endian */
- li t0, AU1500_SYS_ADDR
- li t1, 1
- sw t1, sys_endian(t0)
- mfc0 t2, CP0_CONFIG
- mtc0 t2, CP0_CONFIG
- nop
- nop
-
- /* Big Endian is default so nothing to do but fall through */
-
-big_endian:
-
- /*
- * Step 2) Establish Status Register
- * (set BEV, clear ERL, clear EXL, clear IE)
- */
- li t1, 0x00400000
- mtc0 t1, CP0_STATUS
-
- /*
- * Step 3) Establish CP0 Config0
- * (set OD, set K0=3)
- */
- li t1, 0x00080003
- mtc0 t1, CP0_CONFIG
-
- /*
- * Step 4) Disable Watchpoint facilities
- */
- li t1, 0x00000000
- mtc0 t1, CP0_WATCHLO
- mtc0 t1, CP0_IWATCHLO
- /*
- * Step 5) Disable the performance counters
- */
- mtc0 zero, CP0_PERFORMANCE
- nop
-
- /*
- * Step 6) Establish EJTAG Debug register
- */
- mtc0 zero, CP0_DEBUG
- nop
-
- /*
- * Step 7) Establish Cause
- * (set IV bit)
- */
- li t1, 0x00800000
- mtc0 t1, CP0_CAUSE
-
- /* Establish Wired (and Random) */
- mtc0 zero, CP0_WIRED
- nop
-
- /* First setup pll:s to make serial work ok */
- /* We have a 12 MHz crystal */
- li t0, SYS_CPUPLL
- li t1, 0x21 /* 396 MHz */
- sw t1, 0(t0)
- sync
- nop
- nop
-
- /* wait 1mS for clocks to settle */
- li t1, MEM_1MS
-1: add t1, -1
- bne t1, zero, 1b
- nop
- /* Setup AUX PLL */
- li t0, SYS_AUXPLL
- li t1, 8 /* 96 MHz */
- sw t1, 0(t0) /* aux pll */
- sync
-
- /* Static memory controller */
-
- /* RCE0 8MB AMD29D323 Flash */
- li t0, MEM_STCFG0
- li t1, 0x00001403
- sw t1, 0(t0)
-
- li t0, MEM_STTIME0
- li t1, 0xFFFFFFDD
- sw t1, 0(t0)
-
- li t0, MEM_STADDR0
- li t1, 0x11F83FE0
- sw t1, 0(t0)
-
- /* RCE1 CPLD Board Logic */
- li t0, MEM_STCFG1
- li t1, 0x00000083
- sw t1, 0(t0)
-
- li t0, MEM_STTIME1
- li t1, 0x33030A10
- sw t1, 0(t0)
-
- li t0, MEM_STADDR1
- li t1, 0x11803E40
- sw t1, 0(t0)
-
- /* RCE2 CPLD Board Logic */
- li t0, MEM_STCFG2
- li t1, 0x00000004
- sw t1, 0(t0)
-
- li t0, MEM_STTIME2
- li t1, 0x08061908
- sw t1, 0(t0)
-
- li t0, MEM_STADDR2
- li t1, 0x12A03FC0
- sw t1, 0(t0)
-
- /* RCE3 PCMCIA 250ns */
- li t0, MEM_STCFG3
- li t1, 0x00000002
- sw t1, 0(t0)
-
- li t0, MEM_STTIME3
- li t1, 0x280E3E07
- sw t1, 0(t0)
-
- li t0, MEM_STADDR3
- li t1, 0x10000000
- sw t1, 0(t0)
-
- sync
-
- /* Set peripherals to a known state */
- li t0, IC0_CFG0CLR
- li t1, 0xFFFFFFFF
- sw t1, 0(t0)
-
- li t0, IC0_CFG0CLR
- sw t1, 0(t0)
-
- li t0, IC0_CFG1CLR
- sw t1, 0(t0)
-
- li t0, IC0_CFG2CLR
- sw t1, 0(t0)
-
- li t0, IC0_SRCSET
- sw t1, 0(t0)
-
- li t0, IC0_ASSIGNSET
- sw t1, 0(t0)
-
- li t0, IC0_WAKECLR
- sw t1, 0(t0)
-
- li t0, IC0_RISINGCLR
- sw t1, 0(t0)
-
- li t0, IC0_FALLINGCLR
- sw t1, 0(t0)
-
- li t0, IC0_TESTBIT
- li t1, 0x00000000
- sw t1, 0(t0)
- sync
-
- li t0, IC1_CFG0CLR
- li t1, 0xFFFFFFFF
- sw t1, 0(t0)
-
- li t0, IC1_CFG0CLR
- sw t1, 0(t0)
-
- li t0, IC1_CFG1CLR
- sw t1, 0(t0)
-
- li t0, IC1_CFG2CLR
- sw t1, 0(t0)
-
- li t0, IC1_SRCSET
- sw t1, 0(t0)
-
- li t0, IC1_ASSIGNSET
- sw t1, 0(t0)
-
- li t0, IC1_WAKECLR
- sw t1, 0(t0)
-
- li t0, IC1_RISINGCLR
- sw t1, 0(t0)
-
- li t0, IC1_FALLINGCLR
- sw t1, 0(t0)
-
- li t0, IC1_TESTBIT
- li t1, 0x00000000
- sw t1, 0(t0)
- sync
-
- li t0, SYS_FREQCTRL0
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_FREQCTRL1
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_CLKSRC
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_PININPUTEN
- li t1, 0x00000000
- sw t1, 0(t0)
- sync
-
- li t0, 0xB1100100
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, 0xB1400100
- li t1, 0x00000000
- sw t1, 0(t0)
-
-
- li t0, SYS_WAKEMSK
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_WAKESRC
- li t1, 0x00000000
- sw t1, 0(t0)
-
- /* wait 1mS before setup */
- li t1, MEM_1MS
-1: add t1, -1
- bne t1, zero, 1b
- nop
-
- /*
- * Skip memory setup if we are running from memory
- */
- li t0, 0x90000000
- sub t0, ra, t0
- bltz t0, skip_memsetup
- nop
-
- /*
- * SDCS0 - Not used, for SMROM
- * SDCS1 - 32MB Micron 48LCBM16A2
- * SDCS2 - 32MB Micron 48LCBM16A2
- */
- li t0, MEM_SDMODE0
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, MEM_SDMODE1
- li t1, 0x00552229
- sw t1, 0(t0)
-
- li t0, MEM_SDMODE2
- li t1, 0x00552229
- sw t1, 0(t0)
-
- li t0, MEM_SDADDR0
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, MEM_SDADDR1
- li t1, 0x001003F8
- sw t1, 0(t0)
-
- li t0, MEM_SDADDR2
- li t1, 0x001023F8
- sw t1, 0(t0)
-
- sync
-
- li t0, MEM_SDREFCFG
- li t1, 0x74000c30 /* Disable */
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDPRECMD
- sw zero, 0(t0)
- sync
-
- li t0, MEM_SDAUTOREF
- sw zero, 0(t0)
- sync
- sw zero, 0(t0)
- sync
-
- li t0, MEM_SDREFCFG
- li t1, 0x76000c30 /* Enable */
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD0
- li t1, 0x00000023
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD1
- li t1, 0x00000023
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD2
- li t1, 0x00000023
- sw t1, 0(t0)
- sync
-
- /* wait 1mS after setup */
- li t1, MEM_1MS
-1: add t1, -1
- bne t1, zero, 1b
- nop
-
-skip_memsetup:
-
- li t0, SYS_PINFUNC
- li t1, 0/*0x00008080*/
- sw t1, 0(t0)
-
- /*
- li t0, SYS_TRIOUTCLR
- li t1, 0x00001FFF
- sw t1, 0(t0)
-
- li t0, SYS_OUTPUTCLR
- li t1, 0x00008000
- sw t1, 0(t0)
- */
- sync
-
- jr ra
- nop
diff --git a/board/pb1x00/pb1x00.c b/board/pb1x00/pb1x00.c
deleted file mode 100644
index f3e6110077..0000000000
--- a/board/pb1x00/pb1x00.c
+++ /dev/null
@@ -1,108 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2003
- * Thomas.Lange@corelatus.se
- */
-
-#include <common.h>
-#include <command.h>
-#include <mach/au1x00.h>
-#include <asm/mipsregs.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
- /* Sdram is setup by assembler code */
- /* If memory could be changed, we should return the true value here */
- gd->ram_size = 64 * 1024 * 1024;
-
- return 0;
-}
-
-#define BCSR_PCMCIA_PC0DRVEN 0x0010
-#define BCSR_PCMCIA_PC0RST 0x0080
-
-/* In arch/mips/cpu/cpu.c */
-void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
-
-int checkboard (void)
-{
-#if defined(CONFIG_IDE_PCMCIA) && 0
- u16 status;
-#endif
- /* volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10); */
- volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
- u32 proc_id;
-
- *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
-
- proc_id = read_c0_prid();
-
- switch (proc_id >> 24) {
- case 0:
- puts ("Board: Pb1000\n");
- printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
- (proc_id >> 8) & 0xFF, proc_id & 0xFF);
- break;
- case 1:
- puts ("Board: Pb1500\n");
- printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
- (proc_id >> 8) & 0xFF, proc_id & 0xFF);
- break;
- case 2:
- puts ("Board: Pb1100\n");
- printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
- (proc_id >> 8) & 0xFF, proc_id & 0xFF);
- break;
- default:
- printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
- }
-
- set_io_port_base(0);
-
-#if defined(CONFIG_IDE_PCMCIA) && 0
- /* Enable 3.3 V on slot 0 ( VCC )
- No 5V */
- status = 4;
- *pcmcia_bcsr = status;
-
- status |= BCSR_PCMCIA_PC0DRVEN;
- *pcmcia_bcsr = status;
- au_sync();
-
- udelay(300*1000);
-
- status |= BCSR_PCMCIA_PC0RST;
- *pcmcia_bcsr = status;
- au_sync();
-
- udelay(100*1000);
-
- /* PCMCIA is on a 36 bit physical address.
- We need to map it into a 32 bit addresses */
-
-#if 0
- /* We dont need theese unless we run whole pcmcia package */
- write_one_tlb(20, /* index */
- 0x01ffe000, /* Pagemask, 16 MB pages */
- CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
- 0x3C000017, /* Lo0 */
- 0x3C200017); /* Lo1 */
-
- write_one_tlb(21, /* index */
- 0x01ffe000, /* Pagemask, 16 MB pages */
- CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
- 0x3D000017, /* Lo0 */
- 0x3D200017); /* Lo1 */
-#endif /* 0 */
- write_one_tlb(22, /* index */
- 0x01ffe000, /* Pagemask, 16 MB pages */
- CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */
- 0x3E000017, /* Lo0 */
- 0x3E200017); /* Lo1 */
-#endif /* CONFIG_IDE_PCMCIA */
-
- return 0;
-}