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authorJon Smirl <jonsmirl@gmail.com>2009-06-14 18:21:28 -0400
committerWolfgang Denk <wd@denx.de>2009-07-10 23:21:32 +0200
commitc9969947a4687de90e2bb58e76842b491aa0e0b9 (patch)
tree7bd09807d9660c477ca5fca8b8e5ca8547f1d008 /board/phytec/pcm030/mt46v32m16-75.h
parent3672cd5c3b53d219d33345eebad4e25ad5bf6d52 (diff)
board support patch for phyCORE-MPC5200B-tiny
Add support for the Phytec phyCORE-MPC5200B-tiny. Code originally from Pengutronix.de. Created CONFIG_SYS_ATA_CS_ON_TIMER01 define for when IDE CS is on Timer 0/1 Signed-off-by: Jon Smirl <jonsmirl@gmail.com> Acked-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'board/phytec/pcm030/mt46v32m16-75.h')
-rw-r--r--board/phytec/pcm030/mt46v32m16-75.h37
1 files changed, 37 insertions, 0 deletions
diff --git a/board/phytec/pcm030/mt46v32m16-75.h b/board/phytec/pcm030/mt46v32m16-75.h
new file mode 100644
index 0000000000..d69c09c5e6
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+++ b/board/phytec/pcm030/mt46v32m16-75.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * Eric Schumann, Phytec Messtechnik
+ * adapted for mt46v32m16-75 DDR-RAM
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR 1 /* is DDR */
+
+/* Settings for XLB = 132 MHz */
+
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x71500F00
+#define SDRAM_CONFIG1 0x73711930
+#define SDRAM_CONFIG2 0x47770000
+
+#define SDRAM_TAPDELAY 0x10000000 /* reserved Bit in MPC5200 B3-Step */