Merge tag 'u-boot-rockchip-20200531' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip

- Fix mmc of path after syncfrom kernel dts;
- Add dwc3 host support with DM for rk3399;
- Add usb2phy and typec phy for rockchip platform;
- Migrate board list doc to rockchip.rst;
- Add rk3399 Pinebook Pro board support;
- Update dram_init in board_init and add memory node in SPL;

4 files changed, 99 insertions, 0 deletions

diff --git a/board/pine64/pinebook-pro-rk3399/Kconfig b/board/pine64/pinebook-pro-rk3399/Kconfig
new file mode 100644
index 0000000000..3bb7ca448e
--- /dev/null
+++ b/board/pine64/pinebook-pro-rk3399/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PINEBOOK_PRO_RK3399
+
+config SYS_BOARD
+	default "pinebook-pro-rk3399"
+
+config SYS_VENDOR
+	default "pine64"
+
+config SYS_CONFIG_NAME
+	default "pinebook-pro-rk3399"
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+
+endif
diff --git a/board/pine64/pinebook-pro-rk3399/MAINTAINERS b/board/pine64/pinebook-pro-rk3399/MAINTAINERS
new file mode 100644
index 0000000000..227c1c0bea
--- /dev/null
+++ b/board/pine64/pinebook-pro-rk3399/MAINTAINERS
@@ -0,0 +1,8 @@
+PINEBOOK_PRO
+M:	Peter Robinson <pbrobinson@gmail.com>
+S:	Maintained
+F:	board/pine64/rk3399-pinebook-pro/
+F:	include/configs/rk3399-pinebook-pro.h
+F:	arch/arm/dts/rk3399-pinebook-pro.dts
+F:	arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi
+F:	configs/pinebook-pro-rk3399_defconfig
diff --git a/board/pine64/pinebook-pro-rk3399/Makefile b/board/pine64/pinebook-pro-rk3399/Makefile
new file mode 100644
index 0000000000..2f692a12a6
--- /dev/null
+++ b/board/pine64/pinebook-pro-rk3399/Makefile
@@ -0,0 +1 @@
+obj-y	+= pinebook-pro-rk3399.o
diff --git a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c
new file mode 100644
index 0000000000..516292aaa5
--- /dev/null
+++ b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2020 Peter Robinson <pbrobinson at gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/misc.h>
+#include <power/regulator.h>
+
+#define GRF_IO_VSEL_BT565_SHIFT 0
+#define PMUGRF_CON0_VSEL_SHIFT 8
+
+#ifndef CONFIG_SPL_BUILD
+int board_early_init_f(void)
+{
+	struct udevice *regulator;
+	int ret;
+
+	ret = regulator_get_by_platname("vcc5v0_usb", &regulator);
+	if (ret) {
+		pr_debug("%s vcc5v0_usb init fail! ret %d\n", __func__, ret);
+		goto out;
+	}
+
+	ret = regulator_set_enable(regulator, true);
+	if (ret)
+		pr_debug("%s vcc5v0-host-en-gpio set fail! ret %d\n", __func__, ret);
+
+out:
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+static void setup_iodomain(void)
+{
+	struct rk3399_grf_regs *grf =
+	   syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	struct rk3399_pmugrf_regs *pmugrf =
+	   syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+
+	/* BT565 is in 1.8v domain */
+	rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT);
+
+	/* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */
+	rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
+}
+
+int misc_init_r(void)
+{
+	const u32 cpuid_offset = 0x7;
+	const u32 cpuid_length = 0x10;
+	u8 cpuid[cpuid_length];
+	int ret;
+
+	setup_iodomain();
+
+	ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
+	if (ret)
+		return ret;
+
+	ret = rockchip_cpuid_set(cpuid, cpuid_length);
+	if (ret)
+		return ret;
+
+	return ret;
+}
+#endif