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authorMarek Vasut <marek.vasut+renesas@gmail.com>2017-10-08 20:41:18 +0200
committerMarek Vasut <marex@denx.de>2017-12-09 13:36:27 +0100
commit7387d4c23465d1a997c594e9603326f1a50db78d (patch)
tree2bfc29d33bdc171aefff418995002dd744f43d5d /board/renesas/draak
parentd21f08ba818138ed3f81ab755021bdae28c17690 (diff)
ARM: rmobile: Add R8A77995 D3 Draak board
Add bits to support yet another board, the R8A77995 D3 Draak. The DT file is from Linux 4.15-rc1 , commit b35334447513c14a4dd55a67c269a743d4a4824b . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'board/renesas/draak')
-rw-r--r--board/renesas/draak/Kconfig15
-rw-r--r--board/renesas/draak/MAINTAINERS6
-rw-r--r--board/renesas/draak/Makefile9
-rw-r--r--board/renesas/draak/draak.c133
4 files changed, 163 insertions, 0 deletions
diff --git a/board/renesas/draak/Kconfig b/board/renesas/draak/Kconfig
new file mode 100644
index 0000000000..9106387bb9
--- /dev/null
+++ b/board/renesas/draak/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_DRAAK
+
+config SYS_SOC
+ default "rmobile"
+
+config SYS_BOARD
+ default "draak"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "draak"
+
+endif
diff --git a/board/renesas/draak/MAINTAINERS b/board/renesas/draak/MAINTAINERS
new file mode 100644
index 0000000000..1dbcc2811c
--- /dev/null
+++ b/board/renesas/draak/MAINTAINERS
@@ -0,0 +1,6 @@
+DRAAK BOARD
+M: Marek Vasut <marek.vasut+renesas@gmail.com>
+S: Maintained
+F: board/renesas/draak/
+F: include/configs/draak.h
+F: configs/r8a77995_draak_defconfig
diff --git a/board/renesas/draak/Makefile b/board/renesas/draak/Makefile
new file mode 100644
index 0000000000..604522ebb1
--- /dev/null
+++ b/board/renesas/draak/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/draak/Makefile
+#
+# Copyright (C) 2015 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := draak.o
diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c
new file mode 100644
index 0000000000..acdaaff72a
--- /dev/null
+++ b/board/renesas/draak/draak.c
@@ -0,0 +1,133 @@
+/*
+ * board/renesas/draak/draak.c
+ * This file is Draak board support.
+ *
+ * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
+#include <i2c.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CPGWPCR 0xE6150904
+#define CPGWPR 0xE615090C
+
+#define CLK2MHZ(clk) (clk / 1000 / 1000)
+void s_init(void)
+{
+ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+
+ /* Watchdog init */
+ writel(0xA5A5A500, &rwdt->rwtcsra);
+ writel(0xA5A5A500, &swdt->swtcsra);
+
+ writel(0xA5A50000, CPGWPCR);
+ writel(0xFFFFFFFF, CPGWPR);
+}
+
+#define GSX_MSTP112 BIT(12) /* 3DG */
+#define TMU0_MSTP125 BIT(25) /* secure */
+#define TMU1_MSTP124 BIT(24) /* non-secure */
+#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
+#define DVFS_MSTP926 BIT(26)
+#define HSUSB_MSTP704 BIT(4) /* HSUSB */
+
+int board_early_init_f(void)
+{
+ /* TMU0,1 */ /* which use ? */
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
+
+#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
+ /* DVFS for reset */
+ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
+#endif
+ return 0;
+}
+
+/* SYSC */
+/* R/- 32 Power status register 2(3DG) */
+#define SYSC_PWRSR2 0xE6180100
+/* -/W 32 Power resume control register 2 (3DG) */
+#define SYSC_PWRONCR2 0xE618010C
+
+/* HSUSB block registers */
+#define HSUSB_REG_LPSTS 0xE6590102
+#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
+#define HSUSB_REG_UGCTRL2 0xE6590184
+#define HSUSB_REG_UGCTRL2_USB0SEL 0x30
+#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+ /* USB1 pull-up */
+ setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
+
+ /* Configure the HSUSB block */
+ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
+ /* Choice USB0SEL */
+ clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
+ HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
+ /* low power status */
+ setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ if (fdtdec_setup_memory_size() != 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
+
+ return 0;
+}
+
+#define RST_BASE 0xE6160000
+#define RST_CA57RESCNT (RST_BASE + 0x40)
+#define RST_CA53RESCNT (RST_BASE + 0x44)
+#define RST_RSTOUTCR (RST_BASE + 0x58)
+#define RST_CA57_CODE 0xA5A5000F
+#define RST_CA53_CODE 0x5A5A000F
+
+void reset_cpu(ulong addr)
+{
+ unsigned long midr, cputype;
+
+ asm volatile("mrs %0, midr_el1" : "=r" (midr));
+ cputype = (midr >> 4) & 0xfff;
+
+ if (cputype == 0xd03)
+ writel(RST_CA53_CODE, RST_CA53RESCNT);
+ else if (cputype == 0xd07)
+ writel(RST_CA57_CODE, RST_CA57RESCNT);
+ else
+ hang();
+}