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authorHiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>2018-09-26 16:00:09 +0900
committerMarek Vasut <marex@denx.de>2018-10-18 19:07:47 +0200
commitcf97b2213a60417e030e530d472f25ded49ee5b8 (patch)
tree4bc75bdccd03a4dc11f75eb93eb90f5290c41916 /board/renesas/salvator-x
parentfeaf301f784dd73b1d792bfcf7ee6e6e38ed0476 (diff)
ARM: rmobile: Fix module clock controls refer status on Gen3
When referring to the MSTPSR register, it contains the clock status of SYS, RT, SECURE, and controlling SMSTPCR using this value has the problem of being affected by the RT and SECURE status.This patch changes the reference register to SMSTPCR. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Diffstat (limited to 'board/renesas/salvator-x')
-rw-r--r--board/renesas/salvator-x/salvator-x.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c
index a1a1531663..8b15267d7b 100644
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -39,7 +39,7 @@ int board_early_init_f(void)
{
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
- mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
+ mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
#endif
return 0;
}
@@ -60,7 +60,7 @@ int board_init(void)
setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
/* Configure the HSUSB block */
- mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
+ mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
/* Choice USB0SEL */
clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
HSUSB_REG_UGCTRL2_USB0SEL_EHCI);