diff options
| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2008-12-20 19:29:48 +0100 |
|---|---|---|
| committer | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2009-01-16 10:22:26 +0900 |
| commit | e4430779623af500de1cee7892c379f07ef59813 (patch) | |
| tree | 74942b62e37730488c59603d19f045de10c92c1e /board/renesas/sh7763rdp/lowlevel_init.S | |
| parent | 85cb052ee41675ca361e6a4c69455dc715c8f2d9 (diff) | |
sh: lowlevel_init coding style cleanup
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'board/renesas/sh7763rdp/lowlevel_init.S')
| -rw-r--r-- | board/renesas/sh7763rdp/lowlevel_init.S | 162 |
1 files changed, 81 insertions, 81 deletions
diff --git a/board/renesas/sh7763rdp/lowlevel_init.S b/board/renesas/sh7763rdp/lowlevel_init.S index 2a44eee1ad..715e75fe6a 100644 --- a/board/renesas/sh7763rdp/lowlevel_init.S +++ b/board/renesas/sh7763rdp/lowlevel_init.S @@ -33,17 +33,17 @@ lowlevel_init: - mov.l WDTCSR_A, r1 /* Watchdog Control / Status Register */ - mov.l WDTCSR_D, r0 - mov.l r0, @r1 + mov.l WDTCSR_A, r1 /* Watchdog Control / Status Register */ + mov.l WDTCSR_D, r0 + mov.l r0, @r1 - mov.l WDTST_A, r1 /* Watchdog Stop Time Register */ - mov.l WDTST_D, r0 - mov.l r0, @r1 + mov.l WDTST_A, r1 /* Watchdog Stop Time Register */ + mov.l WDTST_D, r0 + mov.l r0, @r1 - mov.l WDTBST_A, r1 /* 0xFFCC0008 (Watchdog Base Stop Time Register */ - mov.l WDTBST_D, r0 - mov.l r0, @r1 + mov.l WDTBST_A, r1 /* 0xFFCC0008 (Watchdog Base Stop Time Register */ + mov.l WDTBST_D, r0 + mov.l r0, @r1 mov.l CCR_A, r1 /* Address of Cache Control Register */ mov.l CCR_CACHE_ICI_D, r0 /* Instruction Cache Invalidate */ @@ -61,107 +61,107 @@ lowlevel_init: mov.l MSTPCR1_D, r0 mov.l r0, @r1 - mov.l RAMCR_A,r1 - mov.l RAMCR_D,r0 + mov.l RAMCR_A, r1 + mov.l RAMCR_D, r0 mov.l r0, @r1 - mov.l MMSELR_A,r1 - mov.l MMSELR_D,r0 + mov.l MMSELR_A, r1 + mov.l MMSELR_D, r0 synco mov.l r0, @r1 - mov.l @r1,r2 /* execute two reads after setting MMSELR*/ - mov.l @r1,r2 + mov.l @r1, r2 /* execute two reads after setting MMSELR*/ + mov.l @r1, r2 synco /* issue memory read */ - mov.l DDRSD_START_A,r1 /* memory address to read*/ - mov.l @r1,r0 + mov.l DDRSD_START_A, r1 /* memory address to read*/ + mov.l @r1, r0 synco - mov.l MIM8_A,r1 - mov.l MIM8_D,r0 - mov.l r0,@r1 + mov.l MIM8_A, r1 + mov.l MIM8_D, r0 + mov.l r0, @r1 - mov.l MIMC_A,r1 - mov.l MIMC_D1,r0 - mov.l r0,@r1 + mov.l MIMC_A, r1 + mov.l MIMC_D1, r0 + mov.l r0, @r1 - mov.l STRC_A,r1 - mov.l STRC_D,r0 - mov.l r0,@r1 + mov.l STRC_A, r1 + mov.l STRC_D, r0 + mov.l r0, @r1 - mov.l SDR4_A,r1 - mov.l SDR4_D,r0 - mov.l r0,@r1 + mov.l SDR4_A, r1 + mov.l SDR4_D, r0 + mov.l r0, @r1 - mov.l MIMC_A,r1 - mov.l MIMC_D2,r0 - mov.l r0,@r1 + mov.l MIMC_A, r1 + mov.l MIMC_D2, r0 + mov.l r0, @r1 nop nop nop - mov.l SCR4_A,r1 - mov.l SCR4_D3,r0 - mov.l r0,@r1 + mov.l SCR4_A, r1 + mov.l SCR4_D3, r0 + mov.l r0, @r1 - mov.l SCR4_A,r1 - mov.l SCR4_D2,r0 - mov.l r0,@r1 + mov.l SCR4_A, r1 + mov.l SCR4_D2, r0 + mov.l r0, @r1 - mov.l SDMR02000_A,r1 - mov.l SDMR02000_D,r0 - mov.l r0,@r1 + mov.l SDMR02000_A, r1 + mov.l SDMR02000_D, r0 + mov.l r0, @r1 - mov.l SDMR00B08_A,r1 - mov.l SDMR00B08_D,r0 - mov.l r0,@r1 + mov.l SDMR00B08_A, r1 + mov.l SDMR00B08_D, r0 + mov.l r0, @r1 - mov.l SCR4_A,r1 - mov.l SCR4_D2,r0 - mov.l r0,@r1 + mov.l SCR4_A, r1 + mov.l SCR4_D2, r0 + mov.l r0, @r1 - mov.l SCR4_A,r1 - mov.l SCR4_D4,r0 - mov.l r0,@r1 + mov.l SCR4_A, r1 + mov.l SCR4_D4, r0 + mov.l r0, @r1 nop nop nop nop - mov.l SCR4_A,r1 - mov.l SCR4_D4,r0 - mov.l r0,@r1 + mov.l SCR4_A, r1 + mov.l SCR4_D4, r0 + mov.l r0, @r1 nop nop nop nop - mov.l SDMR00308_A,r1 - mov.l SDMR00308_D,r0 - mov.l r0,@r1 + mov.l SDMR00308_A, r1 + mov.l SDMR00308_D, r0 + mov.l r0, @r1 - mov.l MIMC_A,r1 - mov.l MIMC_D3,r0 - mov.l r0,@r1 + mov.l MIMC_A, r1 + mov.l MIMC_D3, r0 + mov.l r0, @r1 - mov.l SCR4_A,r1 - mov.l SCR4_D1,r0 - mov.l DELAY60_D,r3 + mov.l SCR4_A, r1 + mov.l SCR4_D1, r0 + mov.l DELAY60_D, r3 delay_loop_60: - mov.l r0,@r1 + mov.l r0, @r1 dt r3 bf delay_loop_60 nop - mov.l CCR_A, r1 /* Address of Cache Control Register */ - mov.l CCR_CACHE_D_2, r0 - mov.l r0, @r1 + mov.l CCR_A, r1 /* Address of Cache Control Register */ + mov.l CCR_CACHE_D_2, r0 + mov.l r0, @r1 bsc_init: mov.l BCR_A, r1 @@ -172,9 +172,9 @@ bsc_init: mov.l CS0BCR_D, r0 mov.l r0, @r1 - mov.l CS1BCR_A,r1 - mov.l CS1BCR_D,r0 - mov.l r0,@r1 + mov.l CS1BCR_A, r1 + mov.l CS1BCR_D, r0 + mov.l r0, @r1 mov.l CS2BCR_A, r1 mov.l CS2BCR_D, r0 @@ -224,27 +224,27 @@ bsc_init: mov.l CS6PCR_D, r0 mov.l r0, @r1 - mov.l DELAY200_D,r3 + mov.l DELAY200_D, r3 delay_loop_200: dt r3 bf delay_loop_200 nop - mov.l PSEL0_A,r1 - mov.l PSEL0_D,r0 - mov.w r0,@r1 + mov.l PSEL0_A, r1 + mov.l PSEL0_D, r0 + mov.w r0, @r1 - mov.l PSEL1_A,r1 - mov.l PSEL1_D,r0 - mov.w r0,@r1 + mov.l PSEL1_A, r1 + mov.l PSEL1_D, r0 + mov.w r0, @r1 - mov.l ICR0_A,r1 - mov.l ICR0_D,r0 - mov.l r0,@r1 + mov.l ICR0_A, r1 + mov.l ICR0_D, r0 + mov.l r0, @r1 stc sr, r0 /* BL bit off(init=ON) */ - mov.l SR_MASK_D, r1 + mov.l SR_MASK_D, r1 and r1, r0 ldc r0, sr @@ -321,7 +321,7 @@ CS4BCR_D: .long 0x77777670 CS5BCR_D: .long 0x77777670 CS6BCR_D: .long 0x77777670 CS0WCR_D: .long 0x7777770F -CS1WCR_D: .long 0x22000002 +CS1WCR_D: .long 0x22000002 CS2WCR_D: .long 0x7777770F CS4WCR_D: .long 0x7777770F CS5WCR_D: .long 0x7777770F |