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authorChander Kashyap <chander.kashyap@linaro.org>2011-12-18 20:16:32 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-02-12 10:11:29 +0100
commit7336278ea286438bc1c71d00eb178b7e085b5c3a (patch)
tree675eed6014de909ddc971f4a4d7c4e894704a0be /board/samsung/origen/lowlevel_init.S
parentdb68bc2c2de15c6e5066427a2e5024667d886b9a (diff)
Origen: Select SCLKMPLL as FIMD0 parent clock
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'board/samsung/origen/lowlevel_init.S')
-rw-r--r--board/samsung/origen/lowlevel_init.S5
1 files changed, 5 insertions, 0 deletions
diff --git a/board/samsung/origen/lowlevel_init.S b/board/samsung/origen/lowlevel_init.S
index 0eebbfc244..9283201201 100644
--- a/board/samsung/origen/lowlevel_init.S
+++ b/board/samsung/origen/lowlevel_init.S
@@ -158,6 +158,11 @@ system_clock_init:
ldr r2, =CLK_SRC_PERIL0_OFFSET
str r1, [r0, r2]
+ /* FIMD0 */
+ ldr r1, =CLK_SRC_LCD0_VAL
+ ldr r2, =CLK_SRC_LCD0_OFFSET
+ str r1, [r0, r2]
+
/* wait ?us */
mov r1, #0x10000
3: subs r1, r1, #1