diff options
| author | Tom Rix <Tom.Rix@windriver.com> | 2009-10-04 05:40:07 -0500 |
|---|---|---|
| committer | Tom Rix <Tom.Rix@windriver.com> | 2009-10-04 05:40:07 -0500 |
| commit | 4d6c2dd7ed6c6bc4114ca5c7577560ea9ba50bd0 (patch) | |
| tree | 676e49c06682ea211d2d909beb35cee5623d106e /board/sandburst/common/sb_common.c | |
| parent | 300d1137161a47573b0f6504f32371c8065b8d37 (diff) | |
| parent | 1d96cfe8f5eebfc6ea39d1a387f35ca4499e6b67 (diff) | |
Merge branch 'arm/master' into arm/next
Conflicts:
board/AtmarkTechno/suzaku/Makefile
board/amcc/acadia/acadia.c
board/amcc/katmai/katmai.c
board/amcc/luan/luan.c
board/amcc/ocotea/ocotea.c
board/cm-bf537u/Makefile
board/cray/L1/L1.c
board/csb272/csb272.c
board/csb472/csb472.c
board/eric/eric.c
board/eric/init.S
board/eukrea/cpuat91/Makefile
board/exbitgen/exbitgen.c
board/exbitgen/init.S
board/freescale/mpc8536ds/config.mk
board/g2000/g2000.c
board/jse/sdram.c
board/mpl/mip405/mip405.c
board/mpl/pip405/pip405.c
board/netstal/hcu5/hcu5.c
board/netstal/mcu25/mcu25.c
board/sc3/sc3.c
board/w7o/init.S
board/w7o/w7o.c
common/cmd_reginfo.c
cpu/ppc4xx/40x_spd_sdram.c
cpu/ppc4xx/44x_spd_ddr.c
doc/README.sbc8548
drivers/misc/fsl_law.c
fs/ubifs/ubifs.c
include/asm-ppc/immap_85xx.h
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
Diffstat (limited to 'board/sandburst/common/sb_common.c')
| -rw-r--r-- | board/sandburst/common/sb_common.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c index d8b0564b3b..e1c61463dd 100644 --- a/board/sandburst/common/sb_common.c +++ b/board/sandburst/common/sb_common.c @@ -266,11 +266,11 @@ long int fixed_sdram (void) /*-------------------------------------------------------------------- * Setup some default *------------------------------------------------------------------*/ - mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */ - mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ + mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ + mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ + mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ + mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ + mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ /*-------------------------------------------------------------------- * Setup for board-specific specific mem @@ -278,20 +278,20 @@ long int fixed_sdram (void) /* * Following for CAS Latency = 2.5 @ 133 MHz PLB */ - mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ - mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ + mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ + mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ /* RA=10 RD=3 */ - mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ + mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ + mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ + mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */ udelay (400); /* Delay 200 usecs (min) */ /*-------------------------------------------------------------------- * Enable the controller, then wait for DCEN to complete *------------------------------------------------------------------*/ - mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ + mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ for (;;) { - mfsdram (mem_mcsts, reg); + mfsdram (SDRAM0_MCSTS, reg); if (reg & 0x80000000) break; } |