diff options
| author | Marek Vasut <marex@denx.de> | 2017-11-09 11:50:13 +0100 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2017-11-16 10:43:22 +0100 |
| commit | b979e35230042bfeadd5f4eddf66232f29e4bff4 (patch) | |
| tree | 5efda1c4b05b5273352f2d9ba8b201711241d880 /board/schulercontrol/sc_sps_1/spl_boot.c | |
| parent | c253573f3e269fd9a24ee6684d87dd91106018a5 (diff) | |
ARM: imx6: Adjust DDR DRAM settings on DHCOM i.MX6 PDK
The board uses T-topology for the four x16 DRAM chips, so remove
the write-leveling from the SPL as that is only usefly on fly-by
topology and can be harmful on T-topology. Also update the DRAM
timing with values from calibration on multiple boards.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'board/schulercontrol/sc_sps_1/spl_boot.c')
0 files changed, 0 insertions, 0 deletions