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authorWenyou Yang <wenyou.yang@atmel.com>2016-02-03 10:20:45 +0800
committerAndreas Bießmann <andreas.devel@googlemail.com>2016-02-18 21:34:41 +0100
commit30f65c85decb7d6816ba358927ab86e05ccaea2e (patch)
treec178179fe8b270462b71505935c66321196843c1 /board/siemens
parent9cf7385c9b4d33b43dcfb6782f0f246ea33769d9 (diff)
board: atmel: siemens: clean up PLLB code
Due to introducing the new PLLB clock handle functions, use these functions to clean up the PLLB enable code. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Tested-by: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'board/siemens')
-rw-r--r--board/siemens/smartweb/smartweb.c6
-rw-r--r--board/siemens/taurus/taurus.c6
2 files changed, 2 insertions, 10 deletions
diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c
index e7ee65cd8d..47a60a72ac 100644
--- a/board/siemens/smartweb/smartweb.c
+++ b/board/siemens/smartweb/smartweb.c
@@ -115,12 +115,8 @@ static void smartweb_macb_hw_init(void)
void at91_udp_hw_init(void)
{
- at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
-
/* Enable PLLB */
- writel(get_pllb_init(), &pmc->pllbr);
- while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
- ;
+ at91_pllb_clk_enable(get_pllb_init());
/* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
at91_periph_clk_enable(ATMEL_ID_UDP);
diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c
index 9374064df5..b0385d8a6e 100644
--- a/board/siemens/taurus/taurus.c
+++ b/board/siemens/taurus/taurus.c
@@ -289,12 +289,8 @@ void spi_cs_deactivate(struct spi_slave *slave)
void at91_udp_hw_init(void)
{
- at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
-
/* Enable PLLB */
- writel(get_pllb_init(), &pmc->pllbr);
- while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
- ;
+ at91_pllb_clk_enable(get_pllb_init());
/* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
at91_periph_clk_enable(ATMEL_ID_UDP);