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| author | Chris Packham <judge.packham@gmail.com> | 2018-12-03 14:26:49 +1300 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2018-12-08 16:19:40 +0100 |
| commit | ebb1a593252205114f6133b898f67473cc4c4899 (patch) | |
| tree | 8a01f4e39a19bcabcf799b0dbf6935f5d0a66619 /board/solidrun/clearfog/clearfog.c | |
| parent | 3589025867274ff28f689029ab8323301771c8ec (diff) | |
ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02
This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-18.09 branch
of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
Specifically this syncs with commit 99d772547314 ("Bump mv_ddr to
release armada-18.09.2").
The complete log of changes is best obtained from the mv-ddr-marvell.git
repository but some relevant highlights are:
ddr3: add missing txsdll parameter
ddr3: fix tfaw timimg parameter
ddr3: fix trrd timimg parameter
merge ddr3 topology header file with mv_ddr_topology one
mv_ddr: a38x: fix zero memory size scrubbing issue
The upstream code is incorporated omitting the portions not relevant to
Armada-38x and DDR3. After that a semi-automated step is used to drop
unused features with unifdef
find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \
xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \
-UCONFIG_APN806 -UCONFIG_MC_STATIC \
-UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
-UCONFIG_64BIT -UCONFIG_A3700 -UA3900 -UA80X0 \
-UA70X0
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/solidrun/clearfog/clearfog.c')
| -rw-r--r-- | board/solidrun/clearfog/clearfog.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c index 4e1386c8a2..1742aa8921 100644 --- a/board/solidrun/clearfog/clearfog.c +++ b/board/solidrun/clearfog/clearfog.c @@ -65,7 +65,7 @@ static struct mv_ddr_topology_map board_topology_map = { SPEED_BIN_DDR_1600K, /* speed_bin */ MV_DDR_DEV_WIDTH_16BIT, /* memory_width */ MV_DDR_DIE_CAP_4GBIT, /* mem_size */ - DDR_FREQ_800, /* frequency */ + MV_DDR_FREQ_800, /* frequency */ 0, 0, /* cas_wl cas_l */ MV_DDR_TEMP_LOW, /* temperature */ MV_DDR_TIM_DEFAULT} }, /* timing */ |