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| author | Paul Burton <paul.burton@imgtec.com> | 2016-09-21 11:18:58 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2016-09-21 15:04:04 +0200 |
| commit | d608254b0aa23607df1dcb5a7ca07de9a8ec9bb0 (patch) | |
| tree | 08974b3c02079cc147794c9a28eab7f35e0cd156 /board/spear | |
| parent | c5b8412d60e22b49348a63848cbf7b6ab5ccb16e (diff) | |
MIPS: Clear hazard between TagLo writes & cache ops
Writing to the coprocessor 0 TagLo registers introduces an execution
hazard in that we need that write to complete before any cache
instructions execute. Ensure that hazard is cleared by inserting an ehb
instruction between the TagLo writes & cache op loop.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Diffstat (limited to 'board/spear')
0 files changed, 0 insertions, 0 deletions