diff options
| author | Chen-Yu Tsai <wens@csie.org> | 2016-11-30 16:28:34 +0800 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-04-20 13:30:00 +0200 |
| commit | 8094a4a20b05827d6fa91786705b3f6917f7421c (patch) | |
| tree | 883a7ec737ff96f8f6a0ec892870d44129130f86 /board/sunxi | |
| parent | 6c7ae2bfc9f052b89c4a874842a6f44cc2e1f0a9 (diff) | |
sunxi: Add mmc[1-3] pinmux settings for R40
The PIO is generally compatible with the A20, except that it routes the
full 8 bits and eMMC reset pins for mmc2.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'board/sunxi')
| -rw-r--r-- | board/sunxi/board.c | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 4c21180229..04a629125e 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -201,7 +201,8 @@ static void mmc_pinmux_setup(int sdc) case 1: pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) if (pins == SUNXI_GPIO_H) { /* SDC1: PH22-PH-27 */ for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { @@ -296,6 +297,17 @@ static void mmc_pinmux_setup(int sdc) sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); sunxi_gpio_set_drv(SUNXI_GPC(24), 2); } +#elif defined(CONFIG_MACH_SUN8I_R40) + /* SDC2: PC6-PC15, PC24 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + + sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(SUNXI_GPC(24), 2); #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I) /* SDC2: PC5-PC6, PC8-PC16 */ for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { @@ -322,7 +334,8 @@ static void mmc_pinmux_setup(int sdc) case 3: pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) /* SDC3: PI4-PI9 */ for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); |