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authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>2020-01-29 14:08:30 +0300
committerAlexey Brodkin <abrodkin@synopsys.com>2020-02-12 20:47:39 +0300
commitdefd1e71d0e0eaa1af92cadc4a9699830e2f89fc (patch)
tree0908b429e67d6bdd3e5732b64a2be9e82b1de37a /board/synopsys/emsdp
parentb8f3ce013700893a3ed4ae280a2aec0ab95af3de (diff)
CLK: HSDK: fix HDMI clock calculation
HDMI PLL has its own xtal with 27 MHz output but we treat it the same way as other PLLs with 33.33 MHz input. Fix that. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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