diff options
author | Stefan Roese <sr@denx.de> | 2010-05-19 11:11:15 +0200 |
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committer | Stefan Roese <sr@denx.de> | 2010-07-01 10:26:30 +0200 |
commit | 273ed0370d71a91c4e7a047bcfce0df77812f55e (patch) | |
tree | 34c285dd8a54eb08e65457806214df1b65948ef9 /board/t3corp/init.S | |
parent | 4978e6058440b6dc8f8f7498288c06291ba54b13 (diff) |
ppc4xx: Add T3COPR board support (PPC460GT based)
This patch adds support for the T3CORP board, based on the
AppliedMicro (APM) PPC460GT.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/t3corp/init.S')
-rw-r--r-- | board/t3corp/init.S | 99 |
1 files changed, 99 insertions, 0 deletions
diff --git a/board/t3corp/init.S b/board/t3corp/init.S new file mode 100644 index 0000000000..4a4217fc8e --- /dev/null +++ b/board/t3corp/init.S @@ -0,0 +1,99 @@ +/* + * (C) Copyright 2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ppc_asm.tmpl> +#include <config.h> +#include <asm/mmu.h> + +/* + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + */ + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to + * use the speed up boot process. It is patched after relocation to + * enable SA_I + */ + tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, + CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) + + /* + * TLB entries for SDRAM are not needed on this platform. + * They are dynamically generated in the DDR(2) detection + * routine. + */ + +#ifdef CONFIG_SYS_INIT_RAM_DCACHE + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, + AC_RWX | SA_G) +#endif + + tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xc, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xc, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xd, + AC_RW | SA_IG) + + tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xd, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xd, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xd, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xd, + AC_RW | SA_IG) + + /* PCIe UTL register */ + tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xc, AC_RW | SA_IG) + + /* TLB-entry for FPGA(s) */ + tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_1M, CONFIG_SYS_FPGA1_BASE, 4, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_1M, CONFIG_SYS_FPGA2_BASE, 4, + AC_RW | SA_IG) + tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_1M, CONFIG_SYS_FPGA3_BASE, 4, + AC_RW | SA_IG) + + /* TLB-entry for OCM */ + tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, + AC_RWX | SA_I) + + /* TLB-entry for Local Configuration registers => peripherals */ + tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, + CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG) + + tlbtab_end |