diff options
| author | Hans de Goede <hdegoede@redhat.com> | 2015-11-20 19:29:49 +0100 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-12-10 11:14:16 +0100 |
| commit | cbc1a91afb7fb0f096453e5574bc5c0719c6c9c4 (patch) | |
| tree | 9fb14aefe0f3eb502d335f4183b6eb65a71c17b0 /board/terasic/de0-nano-soc/MAINTAINERS | |
| parent | 789fa275b3750e60c60cb3d18eabc9467892c257 (diff) | |
sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs
According to the datasheets the max speed of AHB1 is 276 MHz, so
setting it to PLL6 / 3 which gives us 200MHz everywhere is fine,
and gives us a nice speed-up in certain workloads.
Suggested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'board/terasic/de0-nano-soc/MAINTAINERS')
0 files changed, 0 insertions, 0 deletions