diff options
| author | Tom Rini <trini@konsulko.com> | 2016-10-29 17:16:00 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-10-29 17:16:00 -0400 |
| commit | 4ddc981225288e68d45eb8e33271d1481920086f (patch) | |
| tree | cbba0a7f784d24de94e2ada508e7af4272a9f3a0 /board/terasic | |
| parent | 30aaa774df39971e0f488b7661c8825a45570cd2 (diff) | |
| parent | 4f9378cf67c657c8de20284ed1be8be38a6e47bc (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
Diffstat (limited to 'board/terasic')
| -rw-r--r-- | board/terasic/de0-nano-soc/qts/sdram_config.h | 3 | ||||
| -rw-r--r-- | board/terasic/sockit/qts/sdram_config.h | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/board/terasic/de0-nano-soc/qts/sdram_config.h b/board/terasic/de0-nano-soc/qts/sdram_config.h index 7084797750..d96b28af82 100644 --- a/board/terasic/de0-nano-soc/qts/sdram_config.h +++ b/board/terasic/de0-nano-soc/qts/sdram_config.h @@ -42,6 +42,9 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 #define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 diff --git a/board/terasic/sockit/qts/sdram_config.h b/board/terasic/sockit/qts/sdram_config.h index 769aa77394..99064360b2 100644 --- a/board/terasic/sockit/qts/sdram_config.h +++ b/board/terasic/sockit/qts/sdram_config.h @@ -49,6 +49,9 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF |