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authorJames Doublesin <doublesin@ti.com>2014-12-22 16:26:11 -0600
committerTom Rini <trini@ti.com>2015-01-13 11:53:39 -0500
commitfc46bae2ae38c8d0b1570427b5c9520281eaae4f (patch)
treec2536bc12569eb79405935eaabb2737dfc4e8aac /board/ti/am43xx/board.c
parente2a6207bcc45d9d8f3c2da75d581f3efb4d7e47f (diff)
arm: am437x: Enable hardware leveling for EMIF
Switch to using hardware leveling for certain parameters on the EMIF rather than using precalculated values. Doing this also means we have a common place now between am437x and am335x for setting emif_sdram_ref_ctrl with a value for the correct delay length. Tested-by: Felipe Balbi <balbi@ti.com> Tested-by: Tom Rini <trini@ti.com> Signed-off-by: James Doublesin <doublesin@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'board/ti/am43xx/board.c')
-rw-r--r--board/ti/am43xx/board.c156
1 files changed, 0 insertions, 156 deletions
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 8695fc1790..d851f833aa 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -174,29 +174,6 @@ const struct emif_regs emif_regs_lpddr2 = {
.emif_cos_config = 0x000FFFFF
};
-const u32 ext_phy_ctrl_const_base_lpddr2[] = {
- 0x00500050,
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x40001000,
- 0x08102040
-};
-
const struct ctrl_ioregs ioregs_ddr3 = {
.cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
.cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
@@ -305,139 +282,6 @@ static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
.emif_cos_config = 0x000FFFFF
};
-const u32 ext_phy_ctrl_const_base_ddr3[] = {
- 0x00400040,
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00340034,
- 0x00340034,
- 0x00340034,
- 0x00340034,
- 0x00340034,
- 0x0,
- 0x0,
- 0x40000000,
- 0x08102040
-};
-
-const u32 ext_phy_ctrl_const_base_ddr3_beta[] = {
- 0x00000000,
- 0x00000045,
- 0x00000046,
- 0x00000048,
- 0x00000047,
- 0x00000000,
- 0x0000004C,
- 0x00000070,
- 0x00000085,
- 0x000000A3,
- 0x00000000,
- 0x0000000C,
- 0x00000030,
- 0x00000045,
- 0x00000063,
- 0x00000000,
- 0x0,
- 0x0,
- 0x40000000,
- 0x08102040
-};
-
-const u32 ext_phy_ctrl_const_base_ddr3_production[] = {
- 0x00000000,
- 0x00000044,
- 0x00000044,
- 0x00000046,
- 0x00000046,
- 0x00000000,
- 0x00000059,
- 0x00000077,
- 0x00000093,
- 0x000000A8,
- 0x00000000,
- 0x00000019,
- 0x00000037,
- 0x00000053,
- 0x00000068,
- 0x00000000,
- 0x0,
- 0x0,
- 0x40000000,
- 0x08102040
-};
-
-static const u32 ext_phy_ctrl_const_base_ddr3_sk[] = {
- /* first 5 are taken care by emif_regs */
- 0x00700070,
-
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00350035,
-
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-
- 0x00150015,
- 0x00150015,
- 0x00150015,
- 0x00150015,
- 0x00150015,
-
- 0x00800080,
- 0x00800080,
-
- 0x40000000,
-
- 0x08102040,
-
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
-{
- if (board_is_eposevm()) {
- *regs = ext_phy_ctrl_const_base_lpddr2;
- *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
- } else if (board_is_evm_14_or_later()) {
- *regs = ext_phy_ctrl_const_base_ddr3_production;
- *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_production);
- } else if (board_is_evm_12_or_later()) {
- *regs = ext_phy_ctrl_const_base_ddr3_beta;
- *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_beta);
- } else if (board_is_gpevm()) {
- *regs = ext_phy_ctrl_const_base_ddr3;
- *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
- } else if (board_is_sk()) {
- *regs = ext_phy_ctrl_const_base_ddr3_sk;
- *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_sk);
- }
-
- return;
-}
-
/*
* get_sys_clk_index : returns the index of the sys_clk read from
* ctrl status register. This value is either