diff options
| author | Lokesh Vutla <lokeshvutla@ti.com> | 2013-12-10 15:02:23 +0530 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-12-18 21:14:45 -0500 |
| commit | b5e01eecc89e3e5c2ed3c17b803529be3c3702fb (patch) | |
| tree | 73824a5325ebcf7c0c7cfe28ac5790655f7ca2ca /board/ti/am43xx/mux.c | |
| parent | d3daba10f159cca7e9d24c6f154926a9b92c75e3 (diff) | |
ARM: AM43xx: GP_EVM: Add support for DDR3
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'board/ti/am43xx/mux.c')
| -rw-r--r-- | board/ti/am43xx/mux.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index a2d72dde5f..810b1941db 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -33,6 +33,11 @@ static struct module_pin_mux i2c0_pin_mux[] = { {-1}, }; +static struct module_pin_mux gpio0_22_pin_mux[] = { + {OFFSET(ddr_ba2), (MODE(9) | PULLUP_EN)}, /* GPIO0_22 */ + {-1}, +}; + void enable_uart0_pin_mux(void) { configure_module_pin_mux(uart0_pin_mux); @@ -42,6 +47,9 @@ void enable_board_pin_mux(void) { configure_module_pin_mux(mmc0_pin_mux); configure_module_pin_mux(i2c0_pin_mux); + + if (board_is_gpevm()) + configure_module_pin_mux(gpio0_22_pin_mux); } void enable_i2c0_pin_mux(void) |