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authorLokesh Vutla <lokeshvutla@ti.com>2015-08-17 19:58:34 +0530
committerTom Rini <trini@konsulko.com>2015-08-28 12:33:16 -0400
commit76b3f195e9c771f03161616a2f35ab7070be178a (patch)
tree8e5c622e61bc55ad843e2f7f904e1664b379da2b /board/ti/ks2_evm/board_k2l.c
parentbe8ce70c026e84bb74b4454890b0459d1e484057 (diff)
ARM: k2l: Fix device speeds
ARM supported speeds and init value of core_pll for SDP1200 are programmed wrong as part for the device speed cleanups. Fixing it here. Thanks to "Vitaly Andrianov <vitalya@ti.com>" for bisecting this issue Fixes: c37ed9f11b61 ("ARM: keystone2: Fix dev and arm speed detection") Tested-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'board/ti/ks2_evm/board_k2l.c')
-rw-r--r--board/ti/ks2_evm/board_k2l.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c
index 70e25f10c4..f35a64f2b6 100644
--- a/board/ti/ks2_evm/board_k2l.c
+++ b/board/ti/ks2_evm/board_k2l.c
@@ -25,7 +25,7 @@ unsigned int external_clk[ext_clk_count] = {
static struct pll_init_data core_pll_config[NUM_SPDS] = {
[SPD800] = CORE_PLL_799,
[SPD1000] = CORE_PLL_1000,
- [SPD800] = CORE_PLL_1198,
+ [SPD1200] = CORE_PLL_1198,
};
s16 divn_val[16] = {