diff options
| author | Lokesh Vutla <lokeshvutla@ti.com> | 2017-05-03 16:58:26 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-05-08 12:34:29 -0400 |
| commit | ee3c6532be343e495d11adfe15a457d24d9747d9 (patch) | |
| tree | 202b389517d50e835d6ce1e1a79d7ec2db979e67 /board/ti/ks2_evm/board_k2l.c | |
| parent | c5f177debc8b430c0a0038a9d8f6309eb3bd6299 (diff) | |
ARM: keystone2: Add support for getting external clock dynamically
One some keystone2 platforms like K2G ICE, there is an option
to switch between 24MHz or 25MHz as sysclk. But the existing
driver assumes it is always 24MHz. Add support for getting
all reference clocks dynamically by reading boot pins.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'board/ti/ks2_evm/board_k2l.c')
| -rw-r--r-- | board/ti/ks2_evm/board_k2l.c | 34 |
1 files changed, 27 insertions, 7 deletions
diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c index 2a2e0057e2..f3eea4200c 100644 --- a/board/ti/ks2_evm/board_k2l.c +++ b/board/ti/ks2_evm/board_k2l.c @@ -14,13 +14,33 @@ DECLARE_GLOBAL_DATA_PTR; -unsigned int external_clk[ext_clk_count] = { - [sys_clk] = 122880000, - [alt_core_clk] = 100000000, - [pa_clk] = 122880000, - [tetris_clk] = 122880000, - [ddr3a_clk] = 100000000, -}; +unsigned int get_external_clk(u32 clk) +{ + unsigned int clk_freq; + + switch (clk) { + case sys_clk: + clk_freq = 122880000; + break; + case alt_core_clk: + clk_freq = 100000000; + break; + case pa_clk: + clk_freq = 122880000; + break; + case tetris_clk: + clk_freq = 122880000; + break; + case ddr3a_clk: + clk_freq = 100000000; + break; + default: + clk_freq = 0; + break; + } + + return clk_freq; +} static struct pll_init_data core_pll_config[NUM_SPDS] = { [SPD800] = CORE_PLL_799, |