omap: move TI's boards to board/ti/

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 2009-08-23 16:32:38 +0200
committer: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 2009-09-05 01:33:09 +0200
commit: 0a0e4bad9693ef1d2ca8c33ba551d395a4e3d641 (patch)
tree: 77fe8fd938e959924120b59932cd24c3fecd78cf /board/ti
parent: 2dc851e3b0f07a56f83060f13882ff4b62cf5112 (diff)
32 files changed, 7091 insertions, 0 deletions
diff --git a/board/ti/beagle/Makefile b/board/ti/beagle/Makefile
new file mode 100644
index 0000000000..f7971127c8
--- /dev/null
+++ b/board/ti/beagle/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= beagle.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
new file mode 100644
index 0000000000..32d501e228
--- /dev/null
+++ b/board/ti/beagle/beagle.c
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *	Sunil Kumar <sunilsaini05@gmail.com>
+ *	Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "beagle.h"
+
+static int beagle_revision_c;
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/*
+ * Routine: beagle_get_revision
+ * Description: Return the revision of the BeagleBoard this code is running on.
+ *              If it is a revision Ax/Bx board, this function returns 0,
+ *              on a revision C board you will get a 1.
+ */
+int beagle_get_revision(void)
+{
+	return beagle_revision_c;
+}
+
+/*
+ * Routine: beagle_identify
+ * Description: Detect if we are running on a Beagle revision Ax/Bx or
+ *              Cx. This can be done by GPIO_171. If this is low, we are
+ *              running on a revision C board.
+ */
+void beagle_identify(void)
+{
+	beagle_revision_c = 0;
+	if (!omap_request_gpio(171)) {
+		unsigned int val;
+
+		omap_set_gpio_direction(171, 1);
+		val = omap_get_gpio_datain(171);
+		omap_free_gpio(171);
+
+		if (val)
+			beagle_revision_c = 0;
+		else
+			beagle_revision_c = 1;
+	}
+
+	printf("Board revision ");
+	if (beagle_revision_c)
+		printf("C\n");
+	else
+		printf("Ax/Bx\n");
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+	struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
+
+	twl4030_power_init();
+	twl4030_led_init();
+
+	/* Configure GPIOs to output */
+	writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
+	writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
+		GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
+
+	/* Set GPIOs */
+	writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1,
+		&gpio6_base->setdataout);
+	writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
+		GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
+
+	beagle_identify();
+
+	dieid_num_r();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_BEAGLE();
+
+	if (beagle_revision_c) {
+		MUX_BEAGLE_C();
+	}
+}
diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h
new file mode 100644
index 0000000000..3a0f907d77
--- /dev/null
+++ b/board/ti/beagle/beagle.h
@@ -0,0 +1,384 @@
+/*
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _BEAGLE_H_
+#define _BEAGLE_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_STACKED,
+	"OMAP3 Beagle board",
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
+	"OneNAND",
+#else
+	"NAND",
+#endif
+};
+
+#define BOARD_REVISION_MASK	(0x1 << 11)
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_BEAGLE() \
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0),		(IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1),		(IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2),		(IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3),		(IEN  | PTD | DIS | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4),		(IEN  | PTD | DIS | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5),		(IEN  | PTD | DIS | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6),		(IEN  | PTD | DIS | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7),		(IEN  | PTD | DIS | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
+ MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS3*/\
+ MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS4*/\
+ MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
+ MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
+ MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M1)) /*SYS_nDMA_REQ3*/\
+ MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | DIS | M0)) /*GPMC_nBE1*/\
+ MUX_VAL(CP(GPMC_WAIT2),	(IEN  | PTU | EN  | M0)) /*GPMC_WAIT2*/\
+ MUX_VAL(CP(GPMC_WAIT3),	(IEN  | PTU | EN  | M0)) /*GPMC_WAIT3*/\
+ MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+ MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
+ MUX_VAL(CP(GPMC_WAIT0),	(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT1),	(IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS),	(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+ MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10),	(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11),	(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12),	(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13),	(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14),	(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15),	(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16),	(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17),	(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18),	(IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+ MUX_VAL(CP(DSS_DATA19),	(IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+ MUX_VAL(CP(DSS_DATA20),	(IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+ MUX_VAL(CP(DSS_DATA21),	(IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+ MUX_VAL(CP(DSS_DATA22),	(IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+ MUX_VAL(CP(DSS_DATA23),	(IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+ /*CAMERA*/\
+ MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) /*CAM_HS */\
+ MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) /*CAM_VS */\
+ MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+ MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) /*CAM_D0*/\
+ MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) /*CAM_D1*/\
+ MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) /*CAM_D2*/\
+ MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) /*CAM_D3*/\
+ MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) /*CAM_D4*/\
+ MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) /*CAM_D5*/\
+ MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) /*CAM_D6*/\
+ MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) /*CAM_D7*/\
+ MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) /*CAM_D8*/\
+ MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) /*CAM_D9*/\
+ MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE),	(IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
+ MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
+ MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /*Audio Interface */\
+ MUX_VAL(CP(MCBSP2_FSX),	(IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+ MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card */\
+ MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
+ MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
+ MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
+ MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
+ /*Wireless LAN */\
+ MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M4)) /*GPIO_130*/\
+ MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M4)) /*GPIO_131*/\
+ MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M4)) /*GPIO_132*/\
+ MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M4)) /*GPIO_133*/\
+ MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M4)) /*GPIO_134*/\
+ MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M4)) /*GPIO_135*/\
+ MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M4)) /*GPIO_136*/\
+ MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_137*/\
+ MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | EN  | M4)) /*GPIO_138*/\
+ MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139*/\
+ /*Bluetooth*/\
+ MUX_VAL(CP(MCBSP3_DX),		(IEN  | PTD | DIS | M1)) /*UART2_CTS*/\
+ MUX_VAL(CP(MCBSP3_DR),		(IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+ MUX_VAL(CP(MCBSP3_CLKX),	(IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+ MUX_VAL(CP(MCBSP3_FSX),	(IEN  | PTD | DIS | M1)) /*UART2_RX*/\
+ MUX_VAL(CP(UART2_CTS),		(IEN  | PTD | DIS | M4)) /*GPIO_144*/\
+ MUX_VAL(CP(UART2_RTS),		(IEN  | PTD | DIS | M4)) /*GPIO_145*/\
+ MUX_VAL(CP(UART2_TX),		(IEN  | PTD | DIS | M4)) /*GPIO_146*/\
+ MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M4)) /*GPIO_147*/\
+ /*Modem Interface */\
+ MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+ MUX_VAL(CP(UART1_CTS),		(IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
+ MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX*/\
+ MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
+ MUX_VAL(CP(MCBSP4_DR),		(IEN  | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
+ MUX_VAL(CP(MCBSP4_DX),		(IEN  | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
+ MUX_VAL(CP(MCBSP4_FSX),	(IEN  | PTD | DIS | M1)) /*SSI1_WAKE*/\
+ MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+ MUX_VAL(CP(MCBSP1_FSR),	(IDIS | PTU | EN  | M4)) /*GPIO_157*/\
+ MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_158*/\
+ MUX_VAL(CP(MCBSP1_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+ MUX_VAL(CP(MCBSP_CLKS),	(IEN  | PTU | DIS | M0)) /*McBSP_CLKS*/\
+ MUX_VAL(CP(MCBSP1_FSX),	(IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+ MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+ /*Serial Interface*/\
+ MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0)) /*UART3_CTS_RCTX*/\
+ MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+ MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+ MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ MUX_VAL(CP(HSUSB0_CLK),	(IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP),	(IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT),	(IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M4)) /*GPIO_168*/\
+ MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M4)) /*GPIO_183*/\
+ MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
+ MUX_VAL(CP(HDQ_SIO),		(IDIS | PTU | EN  | M4)) /*GPIO_170*/\
+ MUX_VAL(CP(MCSPI1_CLK),	(IEN  | PTU | EN  | M4)) /*GPIO_171*/\
+ MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTU | EN  | M4)) /*GPIO_172*/\
+ MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) /*McSPI1_SOMI*/\
+ MUX_VAL(CP(MCSPI1_CS0),	(IEN  | PTD | EN  | M0)) /*McSPI1_CS0*/\
+ MUX_VAL(CP(MCSPI1_CS1),	(IDIS | PTD | EN  | M0)) /*McSPI1_CS1*/\
+ MUX_VAL(CP(MCSPI1_CS2),	(IDIS | PTD | DIS | M4)) /*GPIO_176*/\
+ /* USB EHCI (port 2) */\
+ MUX_VAL(CP(MCSPI1_CS3),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA2*/\
+ MUX_VAL(CP(MCSPI2_CLK),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA7*/\
+ MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA4*/\
+ MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA5*/\
+ MUX_VAL(CP(MCSPI2_CS0),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA6*/\
+ MUX_VAL(CP(MCSPI2_CS1),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA3*/\
+ MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\
+ MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\
+ MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DIR*/\
+ MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB2_NXT*/\
+ MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA0*/\
+ MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DATA1*/\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ),	(IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+ MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3*/\
+ MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
+ MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+ MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+ MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
+ MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
+ MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
+ MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M4)) /*GPIO_186*/\
+ MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M3)) /*HSUSB1_STP*/\
+ MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
+ MUX_VAL(CP(ETK_D0_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
+ MUX_VAL(CP(ETK_D1_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
+ MUX_VAL(CP(ETK_D2_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
+ MUX_VAL(CP(ETK_D3_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
+ MUX_VAL(CP(ETK_D4_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
+ MUX_VAL(CP(ETK_D5_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
+ MUX_VAL(CP(ETK_D6_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
+ MUX_VAL(CP(ETK_D7_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
+ MUX_VAL(CP(ETK_D8_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+ MUX_VAL(CP(ETK_D9_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB1_NXT*/\
+ MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
+ MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
+ MUX_VAL(CP(D2D_MCAD3),		(IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
+ MUX_VAL(CP(D2D_MCAD4),		(IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
+ MUX_VAL(CP(D2D_MCAD5),		(IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
+ MUX_VAL(CP(D2D_MCAD6),		(IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
+ MUX_VAL(CP(D2D_MCAD7),		(IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
+ MUX_VAL(CP(D2D_MCAD8),		(IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
+ MUX_VAL(CP(D2D_MCAD9),		(IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
+ MUX_VAL(CP(D2D_MCAD10),	(IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
+ MUX_VAL(CP(D2D_MCAD11),	(IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
+ MUX_VAL(CP(D2D_MCAD12),	(IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
+ MUX_VAL(CP(D2D_MCAD13),	(IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
+ MUX_VAL(CP(D2D_MCAD14),	(IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
+ MUX_VAL(CP(D2D_MCAD15),	(IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
+ MUX_VAL(CP(D2D_MCAD16),	(IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
+ MUX_VAL(CP(D2D_MCAD17),	(IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
+ MUX_VAL(CP(D2D_MCAD18),	(IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
+ MUX_VAL(CP(D2D_MCAD19),	(IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
+ MUX_VAL(CP(D2D_MCAD20),	(IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
+ MUX_VAL(CP(D2D_MCAD21),	(IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
+ MUX_VAL(CP(D2D_MCAD22),	(IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
+ MUX_VAL(CP(D2D_MCAD23),	(IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
+ MUX_VAL(CP(D2D_MCAD24),	(IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
+ MUX_VAL(CP(D2D_MCAD25),	(IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
+ MUX_VAL(CP(D2D_MCAD26),	(IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
+ MUX_VAL(CP(D2D_MCAD27),	(IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
+ MUX_VAL(CP(D2D_MCAD28),	(IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
+ MUX_VAL(CP(D2D_MCAD29),	(IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
+ MUX_VAL(CP(D2D_MCAD30),	(IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
+ MUX_VAL(CP(D2D_MCAD31),	(IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
+ MUX_VAL(CP(D2D_MCAD32),	(IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
+ MUX_VAL(CP(D2D_MCAD33),	(IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
+ MUX_VAL(CP(D2D_MCAD34),	(IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
+ MUX_VAL(CP(D2D_MCAD35),	(IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
+ MUX_VAL(CP(D2D_MCAD36),	(IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
+ MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
+ MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
+ MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) /*d2d_nreswarm */\
+ MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */\
+ MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+ MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) /*d2d_spint*/\
+ MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) /*d2d_frint*/\
+ MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
+ MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
+ MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
+ MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
+ MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+ MUX_VAL(CP(D2D_N3GTDI),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+ MUX_VAL(CP(D2D_N3GTDO),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+ MUX_VAL(CP(D2D_N3GTMS),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
+ MUX_VAL(CP(D2D_N3GTCK),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
+ MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
+ MUX_VAL(CP(D2D_MSTDBY),	(IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
+ MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
+ MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
+ MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
+ MUX_VAL(CP(D2D_MWRITE),	(IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
+ MUX_VAL(CP(D2D_SWRITE),	(IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
+ MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) /*d2d_mread*/\
+ MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /*d2d_sread*/\
+ MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
+ MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
+ MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
+
+#define MUX_BEAGLE_C() \
+ MUX_VAL(CP(MCBSP3_DX),		(IEN | PTD | DIS | M4)) /*GPIO_140*/\
+ MUX_VAL(CP(MCBSP3_DR),		(IEN | PTD | DIS | M4)) /*GPIO_142*/\
+ MUX_VAL(CP(MCBSP3_CLKX),	(IEN | PTD | DIS | M4)) /*GPIO_141*/\
+ MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) /*UART2_CTS*/\
+ MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
+ MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) /*UART2_TX*/
+
+#endif
diff --git a/board/ti/beagle/config.mk b/board/ti/beagle/config.mk
new file mode 100644
index 0000000000..879b2e236f
--- /dev/null
+++ b/board/ti/beagle/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80e80000
diff --git a/board/ti/evm/Makefile b/board/ti/evm/Makefile
new file mode 100644
index 0000000000..b951bb4ed7
--- /dev/null
+++ b/board/ti/evm/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= evm.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/ti/evm/config.mk b/board/ti/evm/config.mk
new file mode 100644
index 0000000000..4d873ebacd
--- /dev/null
+++ b/board/ti/evm/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006 - 2008
+# Texas Instruments, <www.ti.com>
+#
+# EVM uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80e80000
diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
new file mode 100644
index 0000000000..0718a08308
--- /dev/null
+++ b/board/ti/evm/evm.c
@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *	Manikandan Pillai <mani.pillai@ti.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <asm/mach-types.h>
+#include "evm.h"
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+ */
+int misc_init_r(void)
+{
+
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+#if defined(CONFIG_CMD_NET)
+	setup_net_chip();
+#endif
+
+	dieid_num_r();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_EVM();
+}
+
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ *		Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+	struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE;
+	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+	/* Configure GPMC registers */
+	writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
+	writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
+	writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
+	writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
+	writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
+	writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
+	writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
+
+	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+	writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+		&ctrl_base->gpmc_nadv_ale);
+
+	/* Make GPIO 64 as output pin */
+	writel(readl(&gpio3_base->oe) & ~(GPIO0), &gpio3_base->oe);
+
+	/* Now send a pulse on the GPIO pin */
+	writel(GPIO0, &gpio3_base->setdataout);
+	udelay(1);
+	writel(GPIO0, &gpio3_base->cleardataout);
+	udelay(1);
+	writel(GPIO0, &gpio3_base->setdataout);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
diff --git a/board/ti/evm/evm.h b/board/ti/evm/evm.h
new file mode 100644
index 0000000000..4a82a7f441
--- /dev/null
+++ b/board/ti/evm/evm.h
@@ -0,0 +1,393 @@
+/*
+ * (C) Copyright 2008
+ * Nishanth Menon <menon.nishanth@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _EVM_H_
+#define _EVM_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_DISCRETE,
+	"OMAP3 EVM board",
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
+	"OneNAND",
+#else
+	"NAND",
+#endif
+};
+
+static void setup_net_chip(void);
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_EVM() \
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
+ MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS3*/\
+ MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M0)) /*GPMC_nCS4*/\
+ MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS5*/\
+ MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M0)) /*GPMC_nCS6*/\
+ MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M0)) /*GPMC_nCS7*/\
+ MUX_VAL(CP(GPMC_CLK),		(IDIS | PTU | EN  | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0)) /*GPMC_nBE0_CLE*/\
+ MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTU | EN  | M0)) /*GPMC_nBE1*/\
+ MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
+ MUX_VAL(CP(GPMC_WAIT0),	(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT1),	(IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
+ MUX_VAL(CP(GPMC_WAIT2),	(IEN  | PTU | EN  | M4)) /*GPIO_64*/\
+							 /* - ETH_nRESET*/\
+ MUX_VAL(CP(GPMC_WAIT3),	(IEN  | PTU | EN  | M0)) /*GPMC_WAIT3*/\
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+ MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10),	(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11),	(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12),	(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13),	(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14),	(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15),	(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16),	(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17),	(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18),	(IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+ MUX_VAL(CP(DSS_DATA19),	(IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+ MUX_VAL(CP(DSS_DATA20),	(IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+ MUX_VAL(CP(DSS_DATA21),	(IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+ MUX_VAL(CP(DSS_DATA22),	(IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+ MUX_VAL(CP(DSS_DATA23),	(IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+ /*CAMERA*/\
+ MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) /*CAM_HS */\
+ MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) /*CAM_VS */\
+ MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+							 /* - CAM_RESET*/\
+ MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) /*CAM_D0*/\
+ MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) /*CAM_D1*/\
+ MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) /*CAM_D2*/\
+ MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) /*CAM_D3*/\
+ MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) /*CAM_D4*/\
+ MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) /*CAM_D5*/\
+ MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) /*CAM_D6*/\
+ MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) /*CAM_D7*/\
+ MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) /*CAM_D8*/\
+ MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) /*CAM_D9*/\
+ MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE),	(IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
+ MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
+ MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /*Audio Interface */\
+ MUX_VAL(CP(MCBSP2_FSX),	(IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+ MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card  */\
+ MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
+ MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
+ MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
+ MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
+ /*Wireless LAN */\
+ MUX_VAL(CP(MMC2_CLK),		(IEN  | PTD | DIS | M0)) /*MMC2_CLK*/\
+ MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT2*/\
+ MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT3*/\
+ MUX_VAL(CP(MMC2_DAT4),		(IDIS | PTD | DIS | M0)) /*MMC2_DAT4*/\
+ MUX_VAL(CP(MMC2_DAT5),		(IDIS | PTD | DIS | M0)) /*MMC2_DAT5*/\
+ MUX_VAL(CP(MMC2_DAT6),		(IDIS | PTD | DIS | M0)) /*MMC2_DAT6 */\
+ MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT7*/\
+ /*Bluetooth*/\
+ MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\
+ MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M0)) /*McBSP3_DR*/\
+ MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP3_CLKX  */\
+ MUX_VAL(CP(MCBSP3_FSX),	(IEN  | PTD | DIS | M0)) /*McBSP3_FSX*/\
+ MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) /*UART2_CTS*/\
+ MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
+ MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) /*UART2_TX*/\
+ MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M0)) /*UART2_RX*/\
+ /*Modem Interface */\
+ MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
+ MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M0)) /*UART1_CTS*/\
+ MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX*/\
+ MUX_VAL(CP(MCBSP4_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_152*/\
+							 /* - LCD_INI*/\
+ MUX_VAL(CP(MCBSP4_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_153*/\
+							 /* - LCD_ENVDD */\
+ MUX_VAL(CP(MCBSP4_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_154*/\
+							 /* - LCD_QVGA/nVGA */\
+ MUX_VAL(CP(MCBSP4_FSX),	(IDIS | PTD | DIS | M4)) /*GPIO_155*/\
+							 /* - LCD_RESB */\
+ MUX_VAL(CP(MCBSP1_CLKR),	(IEN  | PTD | DIS | M0)) /*MCBSP1_CLKR  */\
+ MUX_VAL(CP(MCBSP1_FSR),	(IDIS | PTU | EN  | M0)) /*MCBSP1_FSR*/\
+ MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M0)) /*MCBSP1_DX*/\
+ MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTD | DIS | M0)) /*MCBSP1_DR*/\
+ MUX_VAL(CP(MCBSP_CLKS),	(IEN  | PTU | DIS | M0)) /*MCBSP_CLKS  */\
+ MUX_VAL(CP(MCBSP1_FSX),	(IEN  | PTD | DIS | M0)) /*MCBSP1_FSX*/\
+ MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTD | DIS | M0)) /*MCBSP1_CLKX  */\
+ /*Serial Interface*/\
+ MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0)) /*UART3_CTS_*/\
+							 /* RCTX*/\
+ MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+ MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+ MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ MUX_VAL(CP(HSUSB0_CLK),	(IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP),	(IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT),	(IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) /*I2C2_SCL*/\
+ MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) /*I2C2_SDA*/\
+ MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
+ MUX_VAL(CP(HDQ_SIO),		(IEN  | PTU | EN  | M0)) /*HDQ_SIO*/\
+ MUX_VAL(CP(MCSPI1_CLK),	(IEN  | PTD | DIS | M0)) /*McSPI1_CLK*/\
+ MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M0)) /*McSPI1_SIMO  */\
+ MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) /*McSPI1_SOMI  */\
+ MUX_VAL(CP(MCSPI1_CS0),	(IEN  | PTD | EN  | M0)) /*McSPI1_CS0*/\
+ MUX_VAL(CP(MCSPI1_CS1),	(IEN  | PTD | EN  | M4)) /*GPIO_175*/\
+							 /* TS_PEN_IRQ */\
+ MUX_VAL(CP(MCSPI1_CS2),	(IEN  | PTU | DIS | M4)) /*GPIO_176*/\
+							 /* - LAN_INTR*/\
+ MUX_VAL(CP(MCSPI1_CS3),	(IEN  | PTD | EN  | M0)) /*McSPI1_CS3*/\
+ MUX_VAL(CP(MCSPI2_CLK),	(IEN  | PTD | DIS | M0)) /*McSPI2_CLK*/\
+ MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0)) /*McSPI2_SIMO*/\
+ MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) /*McSPI2_SOMI*/\
+ MUX_VAL(CP(MCSPI2_CS0),	(IEN  | PTD | EN  | M0)) /*McSPI2_CS0*/\
+ MUX_VAL(CP(MCSPI2_CS1),	(IEN  | PTD | EN  | M0)) /*McSPI2_CS1*/\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ),	(IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+							 /* - PEN_IRQ */\
+ MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3 */\
+ MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4*/\
+ MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+ MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+ MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
+ MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/\
+							 /* - VIO_1V8*/\
+ MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
+ MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0)) /*SYS_CLKOUT2*/\
+ MUX_VAL(CP(JTAG_nTRST),	(IEN  | PTD | DIS | M0)) /*JTAG_nTRST*/\
+ MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) /*JTAG_TCK*/\
+ MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)) /*JTAG_TMS*/\
+ MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)) /*JTAG_TDI*/\
+ MUX_VAL(CP(JTAG_EMU0),		(IEN  | PTD | DIS | M0)) /*JTAG_EMU0*/\
+ MUX_VAL(CP(JTAG_EMU1),		(IEN  | PTD | DIS | M0)) /*JTAG_EMU1*/\
+ MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M0)) /*ETK_CLK*/\
+ MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTD | DIS | M0)) /*ETK_CTL*/\
+ MUX_VAL(CP(ETK_D0_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D0*/\
+ MUX_VAL(CP(ETK_D1_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D1*/\
+ MUX_VAL(CP(ETK_D2_ES2 ),	(IEN  | PTD | EN  | M0)) /*ETK_D2*/\
+ MUX_VAL(CP(ETK_D3_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D3*/\
+ MUX_VAL(CP(ETK_D4_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D4*/\
+ MUX_VAL(CP(ETK_D5_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D5*/\
+ MUX_VAL(CP(ETK_D6_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D6*/\
+ MUX_VAL(CP(ETK_D7_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D7*/\
+ MUX_VAL(CP(ETK_D8_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D8*/\
+ MUX_VAL(CP(ETK_D9_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D9*/\
+ MUX_VAL(CP(ETK_D10_ES2),	(IEN  | PTD | DIS | M0)) /*ETK_D10*/\
+ MUX_VAL(CP(ETK_D11_ES2),	(IEN  | PTD | DIS | M0)) /*ETK_D11*/\
+ MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M0)) /*ETK_D12*/\
+ MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M0)) /*ETK_D13*/\
+ MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M0)) /*ETK_D14*/\
+ MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M0)) /*ETK_D15*/\
+ /*Die to Die */\
+ MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
+ MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
+ MUX_VAL(CP(D2D_MCAD3),		(IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
+ MUX_VAL(CP(D2D_MCAD4),		(IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
+ MUX_VAL(CP(D2D_MCAD5),		(IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
+ MUX_VAL(CP(D2D_MCAD6),		(IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
+ MUX_VAL(CP(D2D_MCAD7),		(IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
+ MUX_VAL(CP(D2D_MCAD8),		(IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
+ MUX_VAL(CP(D2D_MCAD9),		(IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
+ MUX_VAL(CP(D2D_MCAD10),	(IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
+ MUX_VAL(CP(D2D_MCAD11),	(IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
+ MUX_VAL(CP(D2D_MCAD12),	(IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
+ MUX_VAL(CP(D2D_MCAD13),	(IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
+ MUX_VAL(CP(D2D_MCAD14),	(IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
+ MUX_VAL(CP(D2D_MCAD15),	(IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
+ MUX_VAL(CP(D2D_MCAD16),	(IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
+ MUX_VAL(CP(D2D_MCAD17),	(IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
+ MUX_VAL(CP(D2D_MCAD18),	(IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
+ MUX_VAL(CP(D2D_MCAD19),	(IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
+ MUX_VAL(CP(D2D_MCAD20),	(IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
+ MUX_VAL(CP(D2D_MCAD21),	(IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
+ MUX_VAL(CP(D2D_MCAD22),	(IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
+ MUX_VAL(CP(D2D_MCAD23),	(IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
+ MUX_VAL(CP(D2D_MCAD24),	(IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
+ MUX_VAL(CP(D2D_MCAD25),	(IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
+ MUX_VAL(CP(D2D_MCAD26),	(IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
+ MUX_VAL(CP(D2D_MCAD27),	(IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
+ MUX_VAL(CP(D2D_MCAD28),	(IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
+ MUX_VAL(CP(D2D_MCAD29),	(IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
+ MUX_VAL(CP(D2D_MCAD30),	(IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
+ MUX_VAL(CP(D2D_MCAD31),	(IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
+ MUX_VAL(CP(D2D_MCAD32),	(IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
+ MUX_VAL(CP(D2D_MCAD33),	(IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
+ MUX_VAL(CP(D2D_MCAD34),	(IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
+ MUX_VAL(CP(D2D_MCAD35),	(IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
+ MUX_VAL(CP(D2D_MCAD36),	(IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
+ MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
+ MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
+ MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) /*d2d_nreswarm */\
+ MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */\
+ MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+ MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) /*d2d_spint*/\
+ MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) /*d2d_frint*/\
+ MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
+ MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
+ MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
+ MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
+ MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+ MUX_VAL(CP(D2D_N3GTDI),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+ MUX_VAL(CP(D2D_N3GTDO),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+ MUX_VAL(CP(D2D_N3GTMS),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
+ MUX_VAL(CP(D2D_N3GTCK),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
+ MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
+ MUX_VAL(CP(D2D_MSTDBY),	(IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
+ MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
+ MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
+ MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
+ MUX_VAL(CP(D2D_MWRITE),	(IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
+ MUX_VAL(CP(D2D_SWRITE),	(IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
+ MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) /*d2d_mread*/\
+ MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /*d2d_sread*/\
+ MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
+ MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
+ MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTD | DIS | M7)) /*sdrc_cke1*/\
+
+#endif
diff --git a/board/ti/omap1510inn/Makefile b/board/ti/omap1510inn/Makefile
new file mode 100644
index 0000000000..cd222dbc16
--- /dev/null
+++ b/board/ti/omap1510inn/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= omap1510innovator.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ti/omap1510inn/config.mk b/board/ti/omap1510inn/config.mk
new file mode 100644
index 0000000000..9cd74246bc
--- /dev/null
+++ b/board/ti/omap1510inn/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Kshitij Gupta <Kshitij@ti.com>
+#
+# TI Innovator board with OMAP1510 (ARM925T) cpu
+# see http://www.ti.com/ for more information on Texas Insturments
+#
+# Innovator has 1 bank of 256 MB SDRAM
+# Physical Address:
+# 1000'0000 to 2000'0000
+#
+#
+# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000  (mem base + reserved)
+#
+# we load ourself to 1108'0000
+#
+#
+
+
+TEXT_BASE = 0x11080000
diff --git a/board/ti/omap1510inn/lowlevel_init.S b/board/ti/omap1510inn/lowlevel_init.S
new file mode 100644
index 0000000000..1c68e5b816
--- /dev/null
+++ b/board/ti/omap1510inn/lowlevel_init.S
@@ -0,0 +1,396 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ *
+ * -- Some bits of code used from rrload's head_OMAP1510.s --
+ * Copyright (C) 2002 RidgeRun, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1510)
+#include <./configs/omap1510.h>
+#endif
+
+#define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK))
+
+
+_TEXT_BASE:
+	.word	TEXT_BASE        /* sdram load addr from config.mk */
+
+.globl lowlevel_init
+lowlevel_init:
+
+	/*
+	 * Configure 1510 pins functions to match our board.
+	 */
+	ldr     r0, REG_PULL_DWN_CTRL_0
+	ldr     r1, VAL_PULL_DWN_CTRL_0
+	str     r1, [r0]
+	ldr     r0, REG_PULL_DWN_CTRL_1
+	ldr     r1, VAL_PULL_DWN_CTRL_1
+	str     r1, [r0]
+	ldr     r0, REG_PULL_DWN_CTRL_2
+	ldr     r1, VAL_PULL_DWN_CTRL_2
+	str     r1, [r0]
+	ldr     r0, REG_PULL_DWN_CTRL_3
+	ldr     r1, VAL_PULL_DWN_CTRL_3
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_4
+	ldr     r1, VAL_FUNC_MUX_CTRL_4
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_5
+	ldr     r1, VAL_FUNC_MUX_CTRL_5
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_6
+	ldr     r1, VAL_FUNC_MUX_CTRL_6
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_7
+	ldr     r1, VAL_FUNC_MUX_CTRL_7
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_8
+	ldr     r1, VAL_FUNC_MUX_CTRL_8
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_9
+	ldr     r1, VAL_FUNC_MUX_CTRL_9
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_A
+	ldr     r1, VAL_FUNC_MUX_CTRL_A
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_B
+	ldr     r1, VAL_FUNC_MUX_CTRL_B
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_C
+	ldr     r1, VAL_FUNC_MUX_CTRL_C
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_D
+	ldr     r1, VAL_FUNC_MUX_CTRL_D
+	str     r1, [r0]
+	ldr     r0, REG_VOLTAGE_CTRL_0
+	ldr     r1, VAL_VOLTAGE_CTRL_0
+	str     r1, [r0]
+	ldr     r0, REG_TEST_DBG_CTRL_0
+	ldr     r1, VAL_TEST_DBG_CTRL_0
+	str     r1, [r0]
+	ldr     r0, REG_MOD_CONF_CTRL_0
+	ldr     r1, VAL_MOD_CONF_CTRL_0
+	str     r1, [r0]
+
+	/* Move to 1510 mode */
+	ldr     r0, REG_COMP_MODE_CTRL_0
+	ldr     r1, VAL_COMP_MODE_CTRL_0
+	str     r1, [r0]
+
+	/* Set up Traffic Ctlr*/
+	ldr r0, REG_TC_IMIF_PRIO
+	mov r1, #0x0
+	str r1, [r0]
+	ldr r0, REG_TC_EMIFS_PRIO
+	str r1, [r0]
+	ldr r0, REG_TC_EMIFF_PRIO
+	str r1, [r0]
+
+	ldr r0, REG_TC_EMIFS_CONFIG
+	ldr r1, [r0]
+	bic r1, r1, #0x08   /* clear the global power-down enable PDE bit */
+	bic r1, r1, #0x01   /* write protect flash by clearing the WP bit */
+	str r1, [r0]        /* EMIFS GlB Configuration. (value 0x12 most likely) */
+
+	/* Setup some clock domains */
+	ldr r1, =OMAP1510_CLKS
+	ldr r0, REG_ARM_IDLECT2
+	strh r1, [r0]  /* CLKM, Clock domain control. */
+
+	mov r1, #0x01  /* PER_EN bit */
+	ldr r0, REG_ARM_RSTCT2
+	strh r1, [r0]  /* CLKM; Peripheral reset. */
+
+	/* Set CLKM to Sync-Scalable  */
+	/* I supposidly need to enable the dsp clock before switching */
+	mov r1, #0x1000
+	ldr r0, REG_ARM_SYSST
+	strh r1, [r0]
+	mov r0, #0x400
+1:
+	subs r0, r0, #0x1   /* wait for any bubbles to finish */
+	bne 1b
+
+	ldr r1, VAL_ARM_CKCTL  /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
+	ldr r0, REG_ARM_CKCTL
+	strh r1, [r0]
+
+	/* setup DPLL 1 */
+	ldr r1, VAL_DPLL1_CTL
+	ldr r0, REG_DPLL1_CTL
+	strh r1, [r0]
+	ands r1, r1, #0x10  /* Check if PLL is enabled. */
+	beq lock_end        /* Do not look for lock if BYPASS selected */
+2:
+	ldrh r1, [r0]
+	ands r1, r1, #0x01  /* Check the LOCK bit. */
+	beq 2b              /* ...loop until bit goes hi. */
+lock_end:
+
+	/* Set memory timings corresponding to the new clock speed */
+
+	/* Check execution location to determine current execution location
+	 * and branch to appropriate initialization code.
+	 */
+	mov r0, #0x10000000                 /* Load physical SDRAM base. */
+	mov r1, pc                          /* Get current execution location. */
+	/* Zero all but top 6 bits of PC, as they alone detect whether an
+	 * address is in the range 0x1000:0000-0x13ff:ffff, the 64M sized
+	 * valid range for SDRAM on the OMAP 1510/5910.
+	 */
+	and r1, r1, #0xfc000000
+	cmp r1, r0			/* Compare. */
+	beq skip_sdram			/* Skip over EMIF-fast initialization
+					 * if running from SDRAM.
+					 */
+
+	/*
+	 * Delay for SDRAM initialization.
+	 */
+	mov r3, #0x1800                        /* value should be checked */
+3:
+	subs r3, r3, #0x1                     /* Decrement count */
+	bne 3b
+
+	/*
+	 * Set SDRAM control values. Disable refresh before MRS command.
+	 */
+	ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG   /* get good value */
+	bic r3, r0, #0xC                    /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */
+	orr r3, r3, #0x8000000              /* (BIT27) Disable CLK when Power down or Self-Refresh */
+	orr r3, r3, #0x4000000              /* BIT26 Power Down Enable */
+	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
+	str r3, [r2]                        /* Store the passed value with AR disabled. */
+
+	ldr r1, VAL_TC_EMIFF_MRS            /* get MRS value */
+	ldr r2, REG_TC_EMIFF_MRS            /* Point to MRS register. */
+	str r1, [r2]                        /* Store the passed value.*/
+
+	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
+	str r0, [r2]                        /* Store the passed value. */
+
+	/*
+	 * Delay for SDRAM initialization.
+	 */
+	mov r3, #0x1800
+4:
+	subs r3, r3, #1                     /* Decrement count. */
+	bne 4b
+
+skip_sdram:
+
+	/* slow interface */
+	ldr r1, VAL_TC_EMIFS_CS0_CONFIG
+	ldr r0, REG_TC_EMIFS_CS0_CONFIG
+	str r1, [r0] /* Chip Select 0 */
+	ldr r1, VAL_TC_EMIFS_CS1_CONFIG
+	ldr r0, REG_TC_EMIFS_CS1_CONFIG
+	str r1, [r0] /* Chip Select 1 */
+	ldr r1, VAL_TC_EMIFS_CS2_CONFIG
+	ldr r0, REG_TC_EMIFS_CS2_CONFIG
+	str r1, [r0] /* Chip Select 2 */
+	ldr r1, VAL_TC_EMIFS_CS3_CONFIG
+	ldr r0, REG_TC_EMIFS_CS3_CONFIG
+	str r1, [r0] /* Chip Select 3 */
+
+ /* Next, Enable the RS232 Line Drivers in the FPGA. */
+ /* Also, power on the audio CODEC's amplifier here, */
+ /* which will make a noise on the audio output. */
+ /* This is done here instead of in the kernel so there */
+ /* isn't a loud popping noise at the start of each */
+ /* song. */
+ /* Also, disable the CODEC's clocks. */
+ /* omap1510-HelenP1 [specific] */
+
+	ldr r0, REG_FPGA_POWER
+	mov r1, #0
+	ldr r2, REG_FPGA_DIP_SWITCH
+	ldrb r3, [r2]
+	cmp r3, #0x8
+	movne r1, #0x62     /* Enable the RS232 Line Drivers in the EPLD */
+	strb r1, [r0]
+	ldr r0, REG_FPGA_AUDIO
+	mov r1, #0x0     /* Disable sound driver (CODEC clocks) */
+	strb r1, [r0]
+
+	/* back to arch calling code */
+	mov	pc, lr
+
+/* the literal pools origin */
+	.ltorg
+
+/* OMAP configuration registers */
+REG_FUNC_MUX_CTRL_0:		/* 32 bits */
+	.word 0xfffe1000
+REG_FUNC_MUX_CTRL_1:		/* 32 bits */
+	.word 0xfffe1004
+REG_FUNC_MUX_CTRL_2:		/* 32 bits */
+	.word 0xfffe1008
+REG_COMP_MODE_CTRL_0:		/* 32 bits */
+	.word 0xfffe100c
+REG_FUNC_MUX_CTRL_3:		/* 32 bits */
+	.word 0xfffe1010
+REG_FUNC_MUX_CTRL_4:		/* 32 bits */
+	.word 0xfffe1014
+REG_FUNC_MUX_CTRL_5:		/* 32 bits */
+	.word 0xfffe1018
+REG_FUNC_MUX_CTRL_6:		/* 32 bits */
+	.word 0xfffe101c
+REG_FUNC_MUX_CTRL_7:		/* 32 bits */
+	.word 0xfffe1020
+REG_FUNC_MUX_CTRL_8:		/* 32 bits */
+	.word 0xfffe1024
+REG_FUNC_MUX_CTRL_9:		/* 32 bits */
+	.word 0xfffe1028
+REG_FUNC_MUX_CTRL_A:		/* 32 bits */
+	.word 0xfffe102C
+REG_FUNC_MUX_CTRL_B:		/* 32 bits */
+	.word 0xfffe1030
+REG_FUNC_MUX_CTRL_C:		/* 32 bits */
+	.word 0xfffe1034
+REG_FUNC_MUX_CTRL_D:		/* 32 bits */
+	.word 0xfffe1038
+REG_PULL_DWN_CTRL_0:		/* 32 bits */
+	.word 0xfffe1040
+REG_PULL_DWN_CTRL_1:		/* 32 bits */
+	.word 0xfffe1044
+REG_PULL_DWN_CTRL_2:		/* 32 bits */
+	.word 0xfffe1048
+REG_PULL_DWN_CTRL_3:		/* 32 bits */
+	.word 0xfffe104c
+REG_VOLTAGE_CTRL_0:		/* 32 bits */
+	.word 0xfffe1060
+REG_TEST_DBG_CTRL_0:		/* 32 bits */
+	.word 0xfffe1070
+REG_MOD_CONF_CTRL_0:		/* 32 bits */
+	.word 0xfffe1080
+REG_TC_IMIF_PRIO:		/* 32 bits */
+	.word 0xfffecc00
+REG_TC_EMIFS_PRIO:		/* 32 bits */
+	.word 0xfffecc04
+REG_TC_EMIFF_PRIO:		/* 32 bits */
+	.word 0xfffecc08
+REG_TC_EMIFS_CONFIG:		/* 32 bits */
+	.word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
+	.word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
+	.word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
+	.word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
+	.word 0xfffecc1c
+REG_TC_EMIFF_SDRAM_CONFIG:	/* 32 bits */
+	.word 0xfffecc20
+REG_TC_EMIFF_MRS:		/* 32 bits */
+	.word 0xfffecc24
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL:			/* 16 bits */
+	.word 0xfffece00
+REG_ARM_IDLECT2:		/* 16 bits */
+	.word 0xfffece08
+REG_ARM_RSTCT2:			/* 16 bits */
+	.word 0xfffece14
+REG_ARM_SYSST:			/* 16 bits */
+	.word 0xfffece18
+/* DPLL control registers */
+REG_DPLL1_CTL:			/* 16 bits */
+	.word 0xfffecf00
+/* identification code register */
+REG_IDCODE:			/* 32 bits */
+	.word 0xfffed404
+
+/* Innovator specific */
+REG_FPGA_LED_DIGIT:		/* 8 bits (not used on Innovator) */
+	.word 0x08000003
+REG_FPGA_POWER:			/* 8 bits */
+	.word 0x08000005
+REG_FPGA_AUDIO:			/* 8 bits (not used on Innovator) */
+	.word 0x0800000c
+REG_FPGA_DIP_SWITCH:		/* 8 bits (not used on Innovator) */
+	.word 0x0800000e
+
+VAL_COMP_MODE_CTRL_0:
+	.word 0x0000eaef
+VAL_FUNC_MUX_CTRL_4:
+	.word 0x00000000
+VAL_FUNC_MUX_CTRL_5:
+	.word 0x00000000
+VAL_FUNC_MUX_CTRL_6:
+	.word 0x00000001
+VAL_FUNC_MUX_CTRL_7:
+	.word 0x00000000
+VAL_FUNC_MUX_CTRL_8:
+	.word 0x10001200
+VAL_FUNC_MUX_CTRL_9:
+	.word 0x01201012
+VAL_FUNC_MUX_CTRL_A:
+	.word 0x00000248
+VAL_FUNC_MUX_CTRL_B:
+	.word 0x00000248
+VAL_FUNC_MUX_CTRL_C:
+	.word 0x09000000
+VAL_FUNC_MUX_CTRL_D:
+	.word 0x00000000
+VAL_PULL_DWN_CTRL_0:
+	.word 0x11a10000
+VAL_PULL_DWN_CTRL_1:
+	.word 0x2e047fff
+VAL_PULL_DWN_CTRL_2:
+	.word 0xffd603a6
+VAL_PULL_DWN_CTRL_3:
+	.word 0x00003e03
+VAL_VOLTAGE_CTRL_0:
+	.word 0x00000007
+VAL_TEST_DBG_CTRL_0:
+	/*  See Errata 4.13, This works around a SRAM bug, for chips below ES2.5 .
+	 *   This slows down internal SRAM accesses.
+	 */
+	.word 0x00000007
+VAL_MOD_CONF_CTRL_0:
+	.word 0x0b000008
+VAL_ARM_CKCTL:
+	.word 0x010f
+VAL_DPLL1_CTL:
+	.word 0x2710
+VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
+	.word 0x00001149
+VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
+	.word 0x00004158
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x002130b0
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x0000f559
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0x000055f0
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x00003331
+VAL_TC_EMIFF_SDRAM_CONFIG:
+	.word 0x010290fc
+VAL_TC_EMIFF_MRS:
+	.word 0x00000027
diff --git a/board/ti/omap1510inn/omap1510innovator.c b/board/ti/omap1510inn/omap1510innovator.c
new file mode 100644
index 0000000000..8941209510
--- /dev/null
+++ b/board/ti/omap1510inn/omap1510innovator.c
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void flash__init (void);
+static void ether__init (void);
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+			  "subs %0, %1, #1\n"
+			  "bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* arch number of OMAP 1510-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+/* kk - this speeds up your boot a quite a bit.  However to make it
+ *  work, you need make sure your kernel startup flush bug is fixed.
+ *  ... rkw ...
+ */
+	icache_enable ();
+
+	flash__init ();
+	ether__init ();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	/* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */
+	/* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */
+
+	/* setup gpio direction to match board (no floats!) */
+	/**gdir = 0xCFF9; */
+	/**mdir = 0x103F; */
+
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+static void flash__init (void)
+{
+#define CS0_CHIP_SELECT_REG 0xfffecc10
+#define CS3_CHIP_SELECT_REG 0xfffecc1c
+#define EMIFS_GlB_Config_REG 0xfffecc0c
+
+	{
+		unsigned int regval;
+
+		regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
+		regval = regval | 0x0001;	/* Turn off write protection for flash devices. */
+		if (regval & 0x0002) {
+			regval = regval & 0xfffd;	/* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */
+			/* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */
+			/* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */
+			/* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */
+		}
+		*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
+	}
+}
+
+
+/******************************
+ Routine:
+ Description:
+******************************/
+static void ether__init (void)
+{
+#define ETH_CONTROL_REG 0x0800000b
+	/* take the Ethernet controller out of reset and wait
+	 * for the EEPROM load to complete.
+	 */
+	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
+	udelay (3);
+}
+
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
diff --git a/board/ti/omap1610inn/Makefile b/board/ti/omap1610inn/Makefile
new file mode 100644
index 0000000000..1adcad64e0
--- /dev/null
+++ b/board/ti/omap1610inn/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= omap1610innovator.o flash.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ti/omap1610inn/config.mk b/board/ti/omap1610inn/config.mk
new file mode 100644
index 0000000000..1c5b7b5c77
--- /dev/null
+++ b/board/ti/omap1610inn/config.mk
@@ -0,0 +1,26 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Kshitij Gupta <Kshitij@ti.com>
+#
+# TI Innovator board with OMAP1610 (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Innovator has 1 bank of 256 MB SDRAM
+# Physical Address:
+# 1000'0000 to 2000'0000
+#
+#
+# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
+# (mem base + reserved)
+#
+# we load ourself to 1108'0000
+#
+#
+
+
+TEXT_BASE = 0x11080000
diff --git a/board/ti/omap1610inn/flash.c b/board/ti/omap1610inn/flash.c
new file mode 100644
index 0000000000..36200ad854
--- /dev/null
+++ b/board/ti/omap1610inn/flash.c
@@ -0,0 +1,493 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips	   */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)			__swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)			__swab32(x)
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef {
+	unsigned int sector_number;
+	unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+OrgDef OrgIntel_28F256L18T[] = {
+	{4, 32 * 1024},				/* 4 * 32kBytes sectors */
+	{255, 128 * 1024},			/* 255 * 128kBytes sectors */
+};
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+unsigned long flash_init (void);
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+void flash_print_info (flash_info_t * info);
+void flash_unprotect_sectors (FPWV * addr);
+int flash_erase (flash_info_t * info, int s_first, int s_last);
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+void flash_unlock(flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[i]);
+			flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[i]);
+			/* to reset the lock bit */
+			flash_unlock(&flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_unlock(flash_info_t * info)
+{
+	int j;
+	for (j=2;j<CONFIG_SYS_MAX_FLASH_SECT;j++){
+	FPWV *addr = (FPWV *) (info->start[j]);
+	flash_unprotect_sectors (addr);
+	*addr = (FPW) 0x00500050;/* clear status register */
+	*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+	OrgDef *pOrgDef;
+
+	pOrgDef = OrgIntel_28F256L18T;
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			if (i > 255) {
+				info->start[i] = base + (i * 0x8000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base +
+						(i * PHYS_FLASH_SECT_SIZE);
+				info->protect[i] = 0;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F256L18T:
+		printf ("FLASH 28F256L18T\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "	   ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);		/* no or unknown flash	*/
+	}
+
+	mb ();
+	value = addr[1];	/* device ID	    */
+	switch (value) {
+
+	case (FPW) (INTEL_ID_28F256L18T):
+		info->flash_id += FLASH_28F256L18T;
+		info->sector_count = 259;
+		info->size = 0x02000000;
+		break;			/* => 32 MB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/* unprotects a sector for write and erase
+ * on some intel parts, this unprotects the entire chip, but it
+ * wont hurt to call this additional times per sector...
+ */
+void flash_unprotect_sectors (FPWV * addr)
+{
+#define PD_FINTEL_WSMS_READY_MASK    0x0080
+
+	*addr = (FPW) 0x00500050;	/* clear status register */
+
+	/* this sends the clear lock bit command */
+	*addr = (FPW) 0x00600060;
+	*addr = (FPW) 0x00D000D0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+				info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			flash_unprotect_sectors (addr);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;/* clear status register */
+			*addr = (FPW) 0x00200020;/* erase setup */
+			*addr = (FPW) 0x00D000D0;/* erase confirm */
+
+			while (((status =
+				*addr) & (FPW) 0x00800080) !=
+				(FPW) 0x00800080) {
+					if (get_timer_masked () >
+					CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					/* suspend erase     */
+					*addr = (FPW) 0x00B000B0;
+					/* reset to read mode */
+					*addr = (FPW) 0x00FF00FF;
+					rcode = 1;
+					break;
+				}
+			}
+
+			/* clear status register cmd.	*/
+			*addr = (FPW) 0x00500050;
+			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/ti/omap1610inn/lowlevel_init.S b/board/ti/omap1610inn/lowlevel_init.S
new file mode 100644
index 0000000000..e4ed9f3c69
--- /dev/null
+++ b/board/ti/omap1610inn/lowlevel_init.S
@@ -0,0 +1,452 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1610)
+#include <./configs/omap1510.h>
+#endif
+
+
+_TEXT_BASE:
+	.word	TEXT_BASE	/* sdram load addr from config.mk */
+
+.globl lowlevel_init
+lowlevel_init:
+
+
+	/*------------------------------------------------------*
+	 *mask all IRQs by setting all bits in the INTMR default*
+	 *------------------------------------------------------*/
+	mov	r1, #0xffffffff
+	ldr	r0, =REG_IHL1_MIR
+	str	r1, [r0]
+	ldr	r0, =REG_IHL2_MIR
+	str	r1, [r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT1)                   *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT1
+	ldr	r1,	VAL_ARM_IDLECT1
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT2)		        *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT2
+	ldr	r1,	VAL_ARM_IDLECT2
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT3)		        *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT3
+	ldr	r1,	VAL_ARM_IDLECT3
+	str	r1,	[r0]
+
+#ifdef CONFIG_CS_AUTOBOOT		/* do the setup depending on boot mode */
+	ldr	r0, CONF_STATUS
+	ldr	r1, [r0]
+	tst	r1, #0x02
+	beq	disable_wd		/* booting from RAM, skip setup */
+#endif
+
+	mov	r1,	#0x01		/* PER_EN bit */
+	ldr	r0,	REG_ARM_RSTCT2
+	strh	r1,	[r0]		/* CLKM; Peripheral reset. */
+
+	/* Set CLKM to Sync-Scalable	*/
+	/* I supposedly need to enable the dsp clock before switching */
+	mov	r1,	#0x0000
+	ldr	r0,	REG_ARM_SYSST
+	strh	r1,	[r0]
+	mov	r0,	#0x400
+1:
+	subs	r0,	r0,	#0x1	/* wait for any bubbles to finish */
+	bne	1b
+	ldr	r1,	VAL_ARM_CKCTL
+	ldr	r0,	REG_ARM_CKCTL
+	strh	r1,	[r0]
+
+	/* a few nops to let settle */
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	/* setup DPLL 1 */
+	/* Ramp up the clock to 96Mhz */
+	ldr	r1,	VAL_DPLL1_CTL
+	ldr	r0,	REG_DPLL1_CTL
+	strh	r1,	[r0]
+	ands	r1,	r1,	#0x10	/* Check if PLL is enabled. */
+	beq	lock_end	/* Do not look for lock if BYPASS selected */
+2:
+	ldrh	r1,	[r0]
+	ands	r1,	r1,	#0x01	/*	Check the LOCK bit.*/
+	beq 2b			/*	loop until bit goes hi. */
+lock_end:
+
+
+	/*------------------------------------------------------*
+	 * Turn off the watchdog during init...			*
+	 *------------------------------------------------------*/
+disable_wd:
+	ldr	r0,	REG_WATCHDOG
+	ldr	r1,	WATCHDOG_VAL1
+	str	r1,	[r0]
+	ldr	r1,	WATCHDOG_VAL2
+	str	r1,	[r0]
+	ldr	r0,	REG_WSPRDOG
+	ldr	r1,	WSPRDOG_VAL1
+	str	r1,	[r0]
+	ldr	r0,	REG_WWPSDOG
+
+watch1Wait:
+	ldr	r1,	[r0]
+	tst	r1,	#0x10
+	bne	watch1Wait
+
+	ldr	r0,	REG_WSPRDOG
+	ldr	r1,	WSPRDOG_VAL2
+	str	r1,	[r0]
+	ldr	r0,	REG_WWPSDOG
+watch2Wait:
+	ldr	r1,	[r0]
+	tst	r1,	#0x10
+	bne	watch2Wait
+
+
+	/* Set memory timings corresponding to the new clock speed */
+
+	/* Check execution location to determine current execution location
+	 * and branch to appropriate initialization code.
+	 */
+	/* Load physical SDRAM base. */
+	mov	r0,	#0x10000000
+	/* Get current execution location. */
+	mov	r1,	pc
+	/* Compare. */
+	cmp	r1,	r0
+	/* Skip over EMIF-fast initialization if running from SDRAM. */
+	bge	skip_sdram
+
+	/*
+	* Delay for SDRAM initialization.
+	*/
+	mov	r3,	#0x1800		/* value should be checked */
+3:
+	subs	r3,	r3,	#0x1	/* Decrement count */
+	bne	3b
+
+
+	/*
+	 * Set SDRAM control values. Disable refresh before MRS command.
+	 */
+
+	/* mobile ddr operation */
+	ldr	r0,	REG_SDRAM_OPERATION
+	mov	r2,	#07
+	str	r2,	[r0]
+
+	/* config register */
+	ldr	r0,	REG_SDRAM_CONFIG
+	ldr	r1,	SDRAM_CONFIG_VAL
+	str	r1,	[r0]
+
+	/* manual command register */
+	ldr	r0,	REG_SDRAM_MANUAL_CMD
+	/* issue set cke high */
+	mov	r1,	#CMD_SDRAM_CKE_SET_HIGH
+	str	r1,	[r0]
+	/* issue nop */
+	mov	r1,	#CMD_SDRAM_NOP
+	str	r1,	[r0]
+
+	mov	r2,	#0x0100
+waitMDDR1:
+	subs	r2,	r2,	 #1
+	bne	waitMDDR1	/* delay loop */
+
+	/* issue precharge */
+	mov	r1,	#CMD_SDRAM_PRECHARGE
+	str	r1,	[r0]
+
+	/* issue autorefresh x 2 */
+	mov	r1,	#CMD_SDRAM_AUTOREFRESH
+	str	r1,	[r0]
+	str	r1,	[r0]
+
+	/* mrs register ddr mobile */
+	ldr	r0,	REG_SDRAM_MRS
+	mov	r1,	#0x33
+	str	r1,	[r0]
+
+	/* emrs1 low-power register */
+	ldr	r0,	REG_SDRAM_EMRS1
+	/* self refresh on all banks */
+	mov	r1,	#0
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_URD_CONTROL
+	ldr	r1,	DLL_URD_CONTROL_VAL
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_LRD_CONTROL
+	ldr	r1,	DLL_LRD_CONTROL_VAL
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_WRT_CONTROL
+	ldr	r1,	DLL_WRT_CONTROL_VAL
+	str	r1,	[r0]
+
+	/* delay loop */
+	mov	r2,	#0x0100
+waitMDDR2:
+	subs	r2,	r2,	#1
+	bne	waitMDDR2
+
+	/*
+	 * Delay for SDRAM initialization.
+	 */
+	mov	r3,	#0x1800
+4:
+	subs	r3,	r3,	#1	/* Decrement count. */
+	bne	4b
+	b	common_tc
+
+skip_sdram:
+
+	ldr	r0,	REG_SDRAM_CONFIG
+	ldr	r1,	SDRAM_CONFIG_VAL
+	str	r1,	[r0]
+
+common_tc:
+	/* slow interface */
+	ldr	r1,	VAL_TC_EMIFS_CS0_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS0_CONFIG
+	str	r1,	[r0] /* Chip Select 0 */
+
+	ldr	r1,	VAL_TC_EMIFS_CS1_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS1_CONFIG
+	str	r1,	[r0] /* Chip Select 1 */
+	ldr	r1,	VAL_TC_EMIFS_CS3_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS3_CONFIG
+	str	r1,	[r0] /* Chip Select 3 */
+
+#ifdef CONFIG_H2_OMAP1610
+	/* inserting additional 2 clock cycle hold time for LAN */
+	ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
+	ldr	r1,     VAL_TC_EMIFS_CS1_ADVANCED
+	str     r1,     [r0]
+#endif
+	/* Start MPU Timer 1 */
+	ldr	r0,	REG_MPU_LOAD_TIMER
+	ldr	r1,	VAL_MPU_LOAD_TIMER
+	str	r1,	[r0]
+
+	ldr	r0,	REG_MPU_CNTL_TIMER
+	ldr	r1,	VAL_MPU_CNTL_TIMER
+	str	r1,	[r0]
+
+	/* back to arch calling code */
+	mov	pc,	lr
+
+	/* the literal pools origin */
+	.ltorg
+
+#ifdef CONFIG_CS_AUTOBOOT
+CONF_STATUS:
+	.word 0xfffe1130	/* 32 bits */
+#endif
+
+REG_TC_EMIFS_CONFIG:		/* 32 bits */
+	.word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
+	.word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
+	.word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
+	.word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
+	.word 0xfffecc1c
+
+#ifdef CONFIG_H2_OMAP1610
+REG_TC_EMIFS_CS1_ADVANCED:	/* 32 bits */
+	.word 0xfffecc54
+#endif
+
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL:			/* 16 bits */
+	.word 0xfffece00
+
+REG_ARM_IDLECT3:		/* 16 bits */
+	.word 0xfffece24
+REG_ARM_IDLECT2:		/* 16 bits */
+	.word 0xfffece08
+REG_ARM_IDLECT1:		/* 16 bits */
+	.word 0xfffece04
+
+REG_ARM_RSTCT2:			/* 16 bits */
+	.word 0xfffece14
+REG_ARM_SYSST:			/* 16 bits */
+	.word 0xfffece18
+/* DPLL control registers */
+REG_DPLL1_CTL:			/* 16 bits */
+	.word 0xfffecf00
+
+/* Watch Dog register */
+/* secure watchdog stop */
+REG_WSPRDOG:
+	.word 0xfffeb048
+/* watchdog write pending */
+REG_WWPSDOG:
+	.word 0xfffeb034
+
+WSPRDOG_VAL1:
+	.word 0x0000aaaa
+WSPRDOG_VAL2:
+	.word 0x00005555
+
+/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
+ counter @8192 rows, 10 ns, 8 burst */
+REG_SDRAM_CONFIG:
+	.word 0xfffecc20
+
+/* Operation register */
+REG_SDRAM_OPERATION:
+	.word 0xfffecc80
+
+/* Manual command register */
+REG_SDRAM_MANUAL_CMD:
+	.word 0xfffecc84
+
+/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
+REG_SDRAM_MRS:
+	.word 0xfffecc70
+
+/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
+REG_SDRAM_EMRS1:
+	.word 0xfffecc78
+
+/* WRT DLL register */
+REG_DLL_WRT_CONTROL:
+	.word 0xfffecc68
+DLL_WRT_CONTROL_VAL:
+	.word 0x03f00002
+
+/* URD DLL register */
+REG_DLL_URD_CONTROL:
+	.word 0xfffeccc0
+DLL_URD_CONTROL_VAL:
+	.word 0x00800002
+
+/* LRD DLL register */
+REG_DLL_LRD_CONTROL:
+	.word 0xfffecccc
+
+REG_WATCHDOG:
+	.word 0xfffec808
+
+REG_MPU_LOAD_TIMER:
+	.word 0xfffec504
+REG_MPU_CNTL_TIMER:
+	.word 0xfffec500
+
+/* 96 MHz Samsung Mobile DDR */
+SDRAM_CONFIG_VAL:
+	.word 0x001200f4
+
+DLL_LRD_CONTROL_VAL:
+	.word 0x00800002
+
+VAL_ARM_CKCTL:
+	.word 0x3000
+VAL_DPLL1_CTL:
+	.word 0x2830
+
+#ifdef CONFIG_INNOVATOROMAP1610
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x002130b0
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x00001131
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0x000055f0
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x88011131
+#endif
+
+#ifdef CONFIG_H2_OMAP1610
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x00203331
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x8180fff3
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0xf800f22a
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x88011131
+VAL_TC_EMIFS_CS1_ADVANCED:
+	.word 0x00000022
+#endif
+
+VAL_TC_EMIFF_SDRAM_CONFIG:
+	.word 0x010290fc
+VAL_TC_EMIFF_MRS:
+	.word 0x00000027
+
+VAL_ARM_IDLECT1:
+	.word 0x00000400
+
+VAL_ARM_IDLECT2:
+	.word 0x00000886
+VAL_ARM_IDLECT3:
+	.word 0x00000015
+
+WATCHDOG_VAL1:
+	.word 0x000000f5
+WATCHDOG_VAL2:
+	.word 0x000000a0
+
+VAL_MPU_LOAD_TIMER:
+	.word 0xffffffff
+VAL_MPU_CNTL_TIMER:
+	.word 0xffffffa1
+
+/* command values */
+.equ CMD_SDRAM_NOP,		0x00000000
+.equ CMD_SDRAM_PRECHARGE,	0x00000001
+.equ CMD_SDRAM_AUTOREFRESH,	0x00000002
+.equ CMD_SDRAM_CKE_SET_HIGH,	0x00000007
diff --git a/board/ti/omap1610inn/omap1610innovator.c b/board/ti/omap1610inn/omap1610innovator.c
new file mode 100644
index 0000000000..2e04ad4bdd
--- /dev/null
+++ b/board/ti/omap1610inn/omap1610innovator.c
@@ -0,0 +1,304 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_OMAP1610)
+#include <./configs/omap1510.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CS_AUTOBOOT
+unsigned long omap_flash_base;
+#endif
+
+void flash__init (void);
+void ether__init (void);
+void set_muxconf_regs (void);
+void peripheral_power_enable (void);
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	if (machine_is_omap_h2())
+		gd->bd->bi_arch_number = MACH_TYPE_OMAP_H2;
+	else if (machine_is_omap_innovator())
+		gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR;
+	else
+		gd->bd->bi_arch_number = MACH_TYPE_OMAP_GENERIC;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+	/* Configure MUX settings */
+	set_muxconf_regs ();
+	peripheral_power_enable ();
+
+/* this speeds up your boot a quite a bit.  However to make it
+ *  work, you need make sure your kernel startup flush bug is fixed.
+ *  ... rkw ...
+ */
+	icache_enable ();
+
+	flash__init ();
+	ether__init ();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	/* currently empty */
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+void flash__init (void)
+{
+#define EMIFS_GlB_Config_REG 0xfffecc0c
+	unsigned int regval;
+
+#ifdef CONFIG_CS_AUTOBOOT
+	 /* Check swapping of CS0 and CS3, set flash base accordingly */
+	omap_flash_base = ((*((u32 *)OMAP_EMIFS_CONFIG_REG) & 0x02) == 0) ?
+					PHYS_FLASH_1_BM0 : PHYS_FLASH_1_BM1;
+#endif
+	regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
+	/* Turn off write protection for flash devices. */
+	regval = regval | 0x0001;
+	*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
+}
+/*************************************************************
+ Routine:ether__init
+ Description: take the Ethernet controller out of reset and wait
+			   for the EEPROM load to complete.
+*************************************************************/
+void ether__init (void)
+{
+#define ETH_CONTROL_REG 0x0400030b
+
+#ifdef CONFIG_H2_OMAP1610
+	#define LAN_RESET_REGISTER 0x0400001c
+
+	/* The debug board on which the lan chip resides may not be powered
+	 * ON at the same time as the OMAP chip. So wait in a loop until the
+	 * lan reset register (on the debug board) is available (powered on)
+	 * and reset the lan chip.
+	 */
+
+	*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
+	do {
+		*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001;
+		udelay (3);
+	} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001);
+
+	do {
+		*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
+		udelay (3);
+	} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000);
+#endif
+
+	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
+	udelay (3);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+/******************************************************
+ Routine: set_muxconf_regs
+ Description: Setting up the configuration Mux registers
+			  specific to the hardware
+*******************************************************/
+void set_muxconf_regs (void)
+{
+	volatile unsigned int *MuxConfReg;
+	/* set each registers to its reset value; */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
+	/* setup for UART1 */
+	*MuxConfReg &= ~(0x02000000);	/* bit 25 */
+	/* setup for UART2 */
+	*MuxConfReg &= ~(0x01000000);	/* bit 24 */
+	/* Disable Uwire CS Hi-Z */
+	*MuxConfReg |= 0x08000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6);
+	/*setup mux for UART3 */
+	*MuxConfReg |= 0x00000001;	/* bit3, 1, 0 (mux0 5,5,26) */
+	*MuxConfReg &= ~0x0000003e;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8);
+	/* Disable Uwire CS Hi-Z */
+	*MuxConfReg |= 0x00001200;	/*bit 9 for CS0 12 for CS3 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9);
+	/*  Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the  */
+	/*  hardware will actually use TX and RTS based on bit 25 in  */
+	/*  FUNC_MUX_CTRL_0.  I told you this thing was screwy!  */
+	*MuxConfReg |= 0x00201000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C);
+	/* setup for UART2 */
+	/*  Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the  */
+	/*  hardware will actually use TX and RTS based on bit 24 in  */
+	/*  FUNC_MUX_CTRL_0. */
+	*MuxConfReg |= 0x09000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1);
+	*MuxConfReg = 0x00000000;
+	/* mux setup for SD/MMC driver */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2);
+	*MuxConfReg &= 0xFFFE0FFF;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	/* bit 13 for MMC2 XOR_CLK */
+	*MuxConfReg &= ~(0x00002000);
+	/* bit 29 for UART 1 */
+	*MuxConfReg &= ~(0x00002000);
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
+	/* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */
+	*MuxConfReg |= 0x000C0000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL);
+	*MuxConfReg &= ~(0x00000070);
+	*MuxConfReg &= ~(0x00000008);
+	*MuxConfReg |= 0x00000003;
+	*MuxConfReg |= 0x00000180;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	/* bit 17, software controls VBUS */
+	*MuxConfReg &= ~(0x00020000);
+	/* Enable USB 48 and 12M clocks */
+	*MuxConfReg |= 0x00000200;
+	*MuxConfReg &= ~(0x00000180);
+	/*2.75V for MMCSDIO1 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0);
+	*MuxConfReg = 0x00001FE7;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_0);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_1);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_4);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4);
+	*MuxConfReg = 0x00000000;
+	/* Turn on UART2 48 MHZ clock */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	*MuxConfReg |= 0x40000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) USB_OTG_CTRL);
+	/* setup for USB VBus detection OMAP161x */
+	*MuxConfReg |= 0x00040000;	/* bit 18 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
+	/* PullUps for SD/MMC driver */
+	*MuxConfReg |= ~(0xFFFE0FFF);
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0);
+	*MuxConfReg = COMP_MODE_ENABLE;
+}
+
+/******************************************************
+ Routine: peripheral_power_enable
+ Description: Enable the power for UART1
+*******************************************************/
+void peripheral_power_enable (void)
+{
+#define UART1_48MHZ_ENABLE	((unsigned short)0x0200)
+#define SW_CLOCK_REQUEST	((volatile unsigned short *)0xFFFE0834)
+
+	*SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE;
+}
diff --git a/board/ti/omap2420h4/Makefile b/board/ti/omap2420h4/Makefile
new file mode 100644
index 0000000000..f39eef0adb
--- /dev/null
+++ b/board/ti/omap2420h4/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= omap2420h4.o mem.o sys_info.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ti/omap2420h4/config.mk b/board/ti/omap2420h4/config.mk
new file mode 100644
index 0000000000..3edcde0188
--- /dev/null
+++ b/board/ti/omap2420h4/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2004
+# Texas Instruments, <www.ti.com>
+#
+# TI H4 board with OMAP2420 (ARM1136) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0
+# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1) ES2 will be configurable
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80e80000
+
+# Used with full SRAM boot.
+# This is either with a GP system or a signed boot image.
+# easiest, and safest way to go if you can.
+#TEXT_BASE = 0x40270000
+
+
+# Handy to get symbols to debug ROM version.
+#TEXT_BASE = 0x0
+#TEXT_BASE = 0x08000000
+#TEXT_BASE = 0x04000000
diff --git a/board/ti/omap2420h4/lowlevel_init.S b/board/ti/omap2420h4/lowlevel_init.S
new file mode 100644
index 0000000000..9752fc488d
--- /dev/null
+++ b/board/ti/omap2420h4/lowlevel_init.S
@@ -0,0 +1,185 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/omap2420.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+
+_TEXT_BASE:
+	.word	TEXT_BASE	/* sdram load addr from config.mk */
+
+/**************************************************************************
+ * cpy_clk_code: relocates clock code into SRAM where its safer to execute
+ * R1 = SRAM destination address.
+ *************************************************************************/
+.global cpy_clk_code
+ cpy_clk_code:
+	/* Copy DPLL code into SRAM */
+	adr	r0, go_to_speed		/* get addr of clock setting code */
+	mov	r2, #384		/* r2 size to copy (div by 32 bytes) */
+	mov	r1, r1			/* r1 <- dest address (passed in) */
+	add	r2, r2, r0		/* r2 <- source end address */
+next2:
+	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end address [r2]    */
+	bne	next2
+	mov	pc, lr			/* back to caller */
+
+/* ****************************************************************************
+ *  go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
+ *		 -executed from SRAM.
+ *  R0 = PRCM_CLKCFG_CTRL - addr of valid reg
+ *  R1 = CM_CLKEN_PLL - addr dpll ctlr reg
+ *  R2 = dpll value
+ *  R3 = CM_IDLEST_CKGEN - addr dpll lock wait
+ ******************************************************************************/
+.global go_to_speed
+ go_to_speed:
+	sub	sp, sp, #0x4 /* get some stack space */
+	str	r4, [sp]     /* save r4's value */
+
+	/* move into fast relock bypass */
+	ldr	r8, pll_ctl_add
+	mov	r4, #0x2
+	str	r4, [r8]
+	ldr	r4, pll_stat
+block:
+	ldr	r8, [r4]	/* wait for bypass to take effect */
+	and	r8, r8, #0x3
+	cmp	r8, #0x1
+	bne	block
+
+	/* set new dpll dividers _after_ in bypass */
+	ldr	r4, pll_div_add
+	ldr	r8, pll_div_val
+	str	r8, [r4]
+
+	/* now prepare GPMC (flash) for new dpll speed */
+	/* flash needs to be stable when we jump back to it */
+	ldr	r4, cfg3_0_addr
+	ldr	r8, cfg3_0_val
+	str	r8, [r4]
+	ldr	r4, cfg4_0_addr
+	ldr	r8, cfg4_0_val
+	str	r8, [r4]
+	ldr	r4, cfg1_0_addr
+	ldr	r8, [r4]
+	orr	r8, r8, #0x3	 /* up gpmc divider */
+	str	r8, [r4]
+
+	/* setup to 2x loop though code.  The first loop pre-loads the
+	 * icache, the 2nd commits the prcm config, and locks the dpll
+	 */
+	mov	r4, #0x1000	 /* spin spin spin */
+	mov	r8, #0x4	 /* first pass condition & set registers */
+	cmp	r8, #0x4
+2:
+	ldrne	r8, [r3]	 /* DPLL lock check */
+	and	r8, r8, #0x7
+	cmp	r8, #0x2
+	beq	4f
+3:
+	subeq	r8, r8, #0x1
+	streq	r8, [r0]	 /* commit dividers (2nd time) */
+	nop
+lloop1:
+	sub	r4, r4, #0x1	/* Loop currently necessary else bad jumps */
+	nop
+	cmp	r4, #0x0
+	bne	lloop1
+	mov	r4, #0x40000
+	cmp	r8, #0x1
+	nop
+	streq	r2, [r1]	/* lock dpll (2nd time) */
+	nop
+lloop2:
+	sub	r4, r4, #0x1	/* loop currently necessary else bad jumps */
+	nop
+	cmp	r4, #0x0
+	bne	lloop2
+	mov	r4, #0x40000
+	cmp	r8, #0x1
+	nop
+	ldreq	r8, [r3]	 /* get lock condition for dpll */
+	cmp	r8, #0x4	 /* first time though? */
+	bne	2b
+	moveq	r8, #0x2	 /* set to dpll check condition. */
+	beq	3b		 /* if condition not true branch */
+4:
+	ldr	r4, [sp]
+	add	sp, sp, #0x4	 /* return stack space */
+	mov	pc, lr		 /* back to caller, locked */
+
+_go_to_speed: .word go_to_speed
+
+/* these constants need to be close for PIC code */
+cfg3_0_addr:
+    .word  GPMC_CONFIG3_0
+cfg3_0_val:
+    .word  H4_24XX_GPMC_CONFIG3_0
+cfg4_0_addr:
+    .word  GPMC_CONFIG4_0
+cfg4_0_val:
+    .word  H4_24XX_GPMC_CONFIG4_0
+cfg1_0_addr:
+    .word  GPMC_CONFIG1_0
+pll_ctl_add:
+    .word CM_CLKEN_PLL
+pll_stat:
+    .word CM_IDLEST_CKGEN
+pll_div_add:
+    .word CM_CLKSEL1_PLL
+pll_div_val:
+    .word DPLL_VAL	/* DPLL setting (300MHz default) */
+
+.globl lowlevel_init
+lowlevel_init:
+	ldr	sp,	SRAM_STACK
+	str	ip,	[sp]	/* stash old link register */
+	mov	ip,	lr	/* save link reg across call */
+	bl	s_init		/* go setup pll,mux,memory */
+	ldr	ip,	[sp]	/* restore save ip */
+	mov	lr,	ip	/* restore link reg */
+
+	/* map interrupt controller */
+	ldr	r0,	VAL_INTH_SETUP
+	mcr	p15, 0, r0, c15, c2, 4
+
+	/* back to arch calling code */
+	mov	pc,	lr
+
+	/* the literal pools origin */
+	.ltorg
+
+REG_CONTROL_STATUS:
+	.word CONTROL_STATUS
+VAL_INTH_SETUP:
+	.word PERIFERAL_PORT_BASE
+SRAM_STACK:
+	.word LOW_LEVEL_SRAM_STACK
diff --git a/board/ti/omap2420h4/mem.c b/board/ti/omap2420h4/mem.c
new file mode 100644
index 0000000000..c8b4186dc8
--- /dev/null
+++ b/board/ti/omap2420h4/mem.c
@@ -0,0 +1,375 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/omap2420.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+
+/************************************************************
+ * sdelay() - simple spin loop.  Will be constant time as
+ *  its generally used in 12MHz bypass conditions only.  This
+ *  is necessary until timers are accessible.
+ *
+ *  not inline to increase chances its in cache when called
+ *************************************************************/
+void sdelay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*********************************************************************************
+ * prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default).
+ *   -- called from SRAM, or Flash (using temp SRAM stack).
+ *********************************************************************************/
+void prcm_init(void)
+{
+	u32 div;
+	void (*f_lock_pll) (u32, u32, u32, u32);
+	extern void *_end_vect, *_start;
+
+	f_lock_pll = (void *)((u32)&_end_vect - (u32)&_start + SRAM_VECT_CODE);
+
+	__raw_writel(0, CM_FCLKEN1_CORE);	   /* stop all clocks to reduce ringing */
+	__raw_writel(0, CM_FCLKEN2_CORE);	   /* may not be necessary */
+	__raw_writel(0, CM_ICLKEN1_CORE);
+	__raw_writel(0, CM_ICLKEN2_CORE);
+
+	__raw_writel(DPLL_OUT, CM_CLKSEL2_PLL);	/* set DPLL out */
+	__raw_writel(MPU_DIV, CM_CLKSEL_MPU);	/* set MPU divider */
+	__raw_writel(DSP_DIV, CM_CLKSEL_DSP);	/* set dsp and iva dividers */
+	__raw_writel(GFX_DIV, CM_CLKSEL_GFX);	/* set gfx dividers */
+
+	div = BUS_DIV;
+	__raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/Vlnc/SSi dividers */
+	sdelay(1000);
+
+	if(running_in_sram()){
+		/* If running fully from SRAM this is OK.  The Flash bus drops out for just a little.
+		* but then comes back.  If running from Flash this sequence kills you, thus you need
+		* to run it using CONFIG_PARTIAL_SRAM.
+		*/
+		__raw_writel(MODE_BYPASS_FAST, CM_CLKEN_PLL); /* go to bypass, fast relock */
+		wait_on_value(BIT0|BIT1, BIT0, CM_IDLEST_CKGEN, LDELAY); /* wait till in bypass */
+		sdelay(1000);
+		/* set clock selection and dpll dividers. */
+		__raw_writel(DPLL_VAL, CM_CLKSEL1_PLL);	 /* set pll for target rate */
+		__raw_writel(COMMIT_DIVIDERS, PRCM_CLKCFG_CTRL); /* commit dividers */
+		sdelay(10000);
+		__raw_writel(DPLL_LOCK, CM_CLKEN_PLL); /* enable dpll */
+		sdelay(10000);
+		wait_on_value(BIT0|BIT1, BIT1, CM_IDLEST_CKGEN, LDELAY);  /*wait for dpll lock */
+	}else if(running_in_flash()){
+		/* if running from flash, need to jump to small relocated code area in SRAM.
+		 * This is the only safe spot to do configurations from.
+		 */
+		(*f_lock_pll)(PRCM_CLKCFG_CTRL, CM_CLKEN_PLL, DPLL_LOCK, CM_IDLEST_CKGEN);
+	}
+
+	__raw_writel(DPLL_LOCK|APLL_LOCK, CM_CLKEN_PLL);   /* enable apll */
+	wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY);	/* wait for apll lock */
+	sdelay(1000);
+}
+
+/**************************************************************************
+ * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
+ *  command line mem=xyz use all memory with out discontigious support
+ *  compiled in.  Could do it at the ATAG, but there really is two banks...
+ * Called as part of 2nd phase DDR init.
+ **************************************************************************/
+void make_cs1_contiguous(void)
+{
+	u32 size, a_add_low, a_add_high;
+
+	size = get_sdr_cs_size(SDRC_CS0_OSET);
+	size /= SZ_32M;  /* find size to offset CS1 */
+	a_add_high = (size & 3) << 8;   /* set up low field */
+	a_add_low = (size & 0x3C) >> 2; /* set up high field */
+	__raw_writel((a_add_high|a_add_low),SDRC_CS_CFG);
+
+}
+
+/********************************************************
+ *  mem_ok() - test used to see if timings are correct
+ *             for a part. Helps in gussing which part
+ *             we are currently using.
+ *******************************************************/
+u32 mem_ok(void)
+{
+	u32 val1, val2;
+	u32 pattern = 0x12345678;
+
+	__raw_writel(0x0,OMAP2420_SDRC_CS0+0x400);   /* clear pos A */
+	__raw_writel(pattern, OMAP2420_SDRC_CS0);    /* pattern to pos B */
+	__raw_writel(0x0,OMAP2420_SDRC_CS0+4);       /* remove pattern off the bus */
+	val1 = __raw_readl(OMAP2420_SDRC_CS0+0x400); /* get pos A value */
+	val2 = __raw_readl(OMAP2420_SDRC_CS0);       /* get val2 */
+
+	if ((val1 != 0) || (val2 != pattern))        /* see if pos A value changed*/
+		return(0);
+	else
+		return(1);
+}
+
+
+/********************************************************
+ *  sdrc_init() - init the sdrc chip selects CS0 and CS1
+ *  - early init routines, called from flash or
+ *  SRAM.
+ *******************************************************/
+void sdrc_init(void)
+{
+	#define EARLY_INIT 1
+	do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT);  /* only init up first bank here */
+}
+
+/*************************************************************************
+ * do_sdrc_init(): initialize the SDRAM for use.
+ *  -called from low level code with stack only.
+ *  -code sets up SDRAM timing and muxing for 2422 or 2420.
+ *  -optimal settings can be placed here, or redone after i2c
+ *      inspection of board info
+ *
+ *  This is a bit ugly, but should handle all memory moduels
+ *   used with the H4. The first time though this code from s_init()
+ *   we configure the first chip select.  Later on we come back and
+ *   will configure the 2nd chip select if it exists.
+ *
+ **************************************************************************/
+void do_sdrc_init(u32 offset, u32 early)
+{
+	u32 cpu, dllen=0, rev, common=0, cs0=0, pmask=0, pass_type, mtype;
+	sdrc_data_t *sdata;	 /* do not change type */
+	u32 a, b, r;
+
+	static const sdrc_data_t sdrc_2422 =
+	{
+		H4_2422_SDRC_SHARING, H4_2422_SDRC_MDCFG_0_DDR, 0 , H4_2422_SDRC_ACTIM_CTRLA_0,
+		H4_2422_SDRC_ACTIM_CTRLB_0, H4_2422_SDRC_RFR_CTRL, H4_2422_SDRC_MR_0_DDR,
+		0, H4_2422_SDRC_DLLAB_CTRL
+	};
+	static const sdrc_data_t sdrc_2420 =
+	{
+		H4_2420_SDRC_SHARING, H4_2420_SDRC_MDCFG_0_DDR, H4_2420_SDRC_MDCFG_0_SDR,
+		H4_2420_SDRC_ACTIM_CTRLA_0, H4_2420_SDRC_ACTIM_CTRLB_0,
+		H4_2420_SDRC_RFR_CTRL, H4_2420_SDRC_MR_0_DDR, H4_2420_SDRC_MR_0_SDR,
+		H4_2420_SDRC_DLLAB_CTRL
+	};
+
+	if (offset == SDRC_CS0_OSET)
+		cs0 = common = 1;  /* int regs shared between both chip select */
+
+	cpu = get_cpu_type();
+	rev = get_cpu_rev();
+
+	/* warning generated, though code generation is correct. this may bite later,
+	 * but is ok for now. there is only so much C code you can do on stack only
+	 * operation.
+	 */
+	if (cpu == CPU_2422){
+		sdata = (sdrc_data_t *)&sdrc_2422;
+		pass_type = STACKED;
+	} else{
+		sdata = (sdrc_data_t *)&sdrc_2420;
+		pass_type = IP_DDR;
+	}
+
+	__asm__ __volatile__("": : :"memory");  /* limit compiler scope */
+
+	/* u-boot is compiled to run in DDR or SRAM at 8xxxxxxx or 4xxxxxxx.
+	 * If we are running in flash prior to relocation and we use data
+	 * here which is not pc relative we need to get the address correct.
+	 * We need to find the current flash mapping to dress up the initial
+	 * pointer load.  As long as this is const data we should be ok.
+	 */
+	if((early) && running_in_flash()){
+		sdata = (sdrc_data_t *)(((u32)sdata & 0x0003FFFF) | get_gpmc0_base());
+		/* NOR internal boot offset is 0x4000 from xloader signature */
+		if(running_from_internal_boot())
+			sdata = (sdrc_data_t *)((u32)sdata + 0x4000);
+	}
+
+	if (!early && (((mtype = get_mem_type()) == DDR_COMBO)||(mtype == DDR_STACKED))) {
+		if(mtype == DDR_COMBO){
+			pmask = BIT2;/* combo part has a shared CKE signal, can't use feature */
+			pass_type = COMBO_DDR; /* CS1 config */
+			__raw_writel((__raw_readl(SDRC_POWER)) & ~pmask, SDRC_POWER);
+		}
+		if(rev != CPU_2420_2422_ES1)	/* for es2 and above smooth things out */
+			make_cs1_contiguous();
+	}
+
+next_mem_type:
+	if (common) {	/* do a SDRC reset between types to clear regs*/
+		__raw_writel(SOFTRESET, SDRC_SYSCONFIG);	/* reset sdrc */
+		wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);/* wait till reset done set */
+		__raw_writel(0, SDRC_SYSCONFIG);		/* clear soft reset */
+		__raw_writel(sdata->sdrc_sharing, SDRC_SHARING);
+#ifdef POWER_SAVE
+		__raw_writel(__raw_readl(SMS_SYSCONFIG)|SMART_IDLE, SMS_SYSCONFIG);
+		__raw_writel(sdata->sdrc_sharing|SMART_IDLE, SDRC_SHARING);
+		__raw_writel((__raw_readl(SDRC_POWER)|BIT6), SDRC_POWER);
+#endif
+	}
+
+	if ((pass_type == IP_DDR) || (pass_type == STACKED)) /* (IP ddr-CS0),(2422-CS0/CS1) */
+		__raw_writel(sdata->sdrc_mdcfg_0_ddr, SDRC_MCFG_0+offset);
+	else if (pass_type == COMBO_DDR){ /* (combo-CS0/CS1) */
+		__raw_writel(H4_2420_COMBO_MDCFG_0_DDR,SDRC_MCFG_0+offset);
+	} else if (pass_type == IP_SDR){ /* ip sdr-CS0 */
+		__raw_writel(sdata->sdrc_mdcfg_0_sdr, SDRC_MCFG_0+offset);
+	}
+
+	a = sdata->sdrc_actim_ctrla_0;
+	b = sdata->sdrc_actim_ctrlb_0;
+	r = sdata->sdrc_dllab_ctrl;
+
+	/* work around ES1 DDR issues */
+	if((pass_type != IP_SDR) && (rev == CPU_2420_2422_ES1)){
+		a = H4_242x_SDRC_ACTIM_CTRLA_0_ES1;
+		b = H4_242x_SDRC_ACTIM_CTRLB_0_ES1;
+		r = H4_242x_SDRC_RFR_CTRL_ES1;
+	}
+
+	if (cs0) {
+		__raw_writel(a, SDRC_ACTIM_CTRLA_0);
+		__raw_writel(b, SDRC_ACTIM_CTRLB_0);
+	} else {
+		__raw_writel(a, SDRC_ACTIM_CTRLA_1);
+		__raw_writel(b, SDRC_ACTIM_CTRLB_1);
+	}
+	__raw_writel(r, SDRC_RFR_CTRL+offset);
+
+	/* init sequence for mDDR/mSDR using manual commands (DDR is a bit different) */
+	__raw_writel(CMD_NOP, SDRC_MANUAL_0+offset);
+	sdelay(5000);  /* susposed to be 100us per design spec for mddr/msdr */
+	__raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0+offset);
+	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset);
+	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset);
+
+	/*
+	 * CSx SDRC Mode Register
+	 * Burst length = (4 - DDR) (2-SDR)
+	 * Serial mode
+	 * CAS latency = x
+	 */
+	if(pass_type == IP_SDR)
+		__raw_writel(sdata->sdrc_mr_0_sdr, SDRC_MR_0+offset);
+	else
+		__raw_writel(sdata->sdrc_mr_0_ddr, SDRC_MR_0+offset);
+
+	/* NOTE: ES1 242x _BUG_ DLL + External Bandwidth fix*/
+	if (rev == CPU_2420_2422_ES1){
+		dllen = (BIT0|BIT3); /* es1 clear both bit0 and bit3 */
+		__raw_writel((__raw_readl(SMS_CLASS_ARB0)|BURSTCOMPLETE_GROUP7)
+			,SMS_CLASS_ARB0);/* enable bust complete for lcd */
+	}
+	else
+		dllen = BIT0|BIT1; /* es2, clear bit0, and 1 (set phase to 72) */
+
+	/* enable & load up DLL with good value for 75MHz, and set phase to 90
+	 * ES1 recommends 90 phase, ES2 recommends 72 phase.
+	 */
+	if (common && (pass_type != IP_SDR)) {
+		__raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLA_CTRL);
+		__raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen), SDRC_DLLA_CTRL);
+		__raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLB_CTRL);
+		__raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen) , SDRC_DLLB_CTRL);
+	}
+	sdelay(90000);
+
+	if(mem_ok())
+		return; /* STACKED, other configued type */
+	++pass_type; /* IPDDR->COMBODDR->IPSDR for CS0 */
+	goto next_mem_type;
+}
+
+/*****************************************************
+ * gpmc_init(): init gpmc bus
+ * Init GPMC for x16, MuxMode (SDRAM in x32).
+ * This code can only be executed from SRAM or SDRAM.
+ *****************************************************/
+void gpmc_init(void)
+{
+	u32 mux=0, mtype, mwidth, rev, tval;
+
+	rev  = get_cpu_rev();
+	if (rev == CPU_2420_2422_ES1)
+		tval = 1;
+	else
+		tval = 0;  /* disable bit switched meaning */
+
+	/* global settings */
+	__raw_writel(0x10, GPMC_SYSCONFIG);	/* smart idle */
+	__raw_writel(0x0, GPMC_IRQENABLE);	/* isr's sources masked */
+	__raw_writel(tval, GPMC_TIMEOUT_CONTROL);/* timeout disable */
+#ifdef CONFIG_SYS_NAND_BOOT
+	__raw_writel(0x001, GPMC_CONFIG);	/* set nWP, disable limited addr */
+#else
+	__raw_writel(0x111, GPMC_CONFIG);	/* set nWP, disable limited addr */
+#endif
+
+	/* discover bus connection from sysboot */
+	if (is_gpmc_muxed() == GPMC_MUXED)
+		mux = BIT9;
+	mtype = get_gpmc0_type();
+	mwidth = get_gpmc0_width();
+
+	/* setup cs0 */
+	__raw_writel(0x0, GPMC_CONFIG7_0);	/* disable current map */
+	sdelay(1000);
+
+#ifdef CONFIG_SYS_NAND_BOOT
+	__raw_writel(H4_24XX_GPMC_CONFIG1_0|mtype|mwidth, GPMC_CONFIG1_0);
+#else
+	__raw_writel(H4_24XX_GPMC_CONFIG1_0|mux|mtype|mwidth, GPMC_CONFIG1_0);
+#endif
+
+#ifdef PRCM_CONFIG_III
+	__raw_writel(H4_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
+#endif
+	__raw_writel(H4_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
+	__raw_writel(H4_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
+#ifdef PRCM_CONFIG_III
+	__raw_writel(H4_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
+	__raw_writel(H4_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0);
+#endif
+	__raw_writel(H4_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);/* enable new mapping */
+	sdelay(2000);
+
+	/* setup cs1 */
+	__raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */
+	sdelay(1000);
+	__raw_writel(H4_24XX_GPMC_CONFIG1_1|mux, GPMC_CONFIG1_1);
+	__raw_writel(H4_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1);
+	__raw_writel(H4_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1);
+	__raw_writel(H4_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1);
+	__raw_writel(H4_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1);
+	__raw_writel(H4_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1);
+	__raw_writel(H4_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1); /* enable mapping */
+	sdelay(2000);
+}
diff --git a/board/ti/omap2420h4/omap2420h4.c b/board/ti/omap2420h4/omap2420h4.c
new file mode 100644
index 0000000000..8d1823900c
--- /dev/null
+++ b/board/ti/omap2420h4/omap2420h4.c
@@ -0,0 +1,844 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/omap2420.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <asm/arch/mem.h>
+#include <i2c.h>
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void wait_for_command_complete(unsigned int wd_base);
+
+/*******************************************************
+ * Routine: delay
+ * Description: spinning delay to use before udelay works
+ ******************************************************/
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*****************************************
+ * Routine: board_init
+ * Description: Early hardware init.
+ *****************************************/
+int board_init (void)
+{
+	gpmc_init(); /* in SRAM or SDRM, finish GPMC */
+
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4;		/* board id for linux */
+	gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0+0x100);	/* adress of boot parameters */
+
+	return 0;
+}
+
+/**********************************************************
+ * Routine: try_unlock_sram()
+ * Description: If chip is GP type, unlock the SRAM for
+ *  general use.
+ ***********************************************************/
+void try_unlock_sram(void)
+{
+	/* if GP device unlock device SRAM for general use */
+	if (get_device_type() == GP_DEVICE) {
+		__raw_writel(0xFF, A_REQINFOPERM0);
+		__raw_writel(0xCFDE, A_READPERM0);
+		__raw_writel(0xCFDE, A_WRITEPERM0);
+	}
+}
+
+/**********************************************************
+ * Routine: s_init
+ * Description: Does early system init of muxing and clocks.
+ * - Called path is with sram stack.
+ **********************************************************/
+void s_init(void)
+{
+	int in_sdram = running_in_sdram();
+
+	watchdog_init();
+	set_muxconf_regs();
+	delay(100);
+	try_unlock_sram();
+
+	if(!in_sdram)
+		prcm_init();
+
+	peripheral_enable();
+	icache_enable();
+	if (!in_sdram)
+		sdrc_init();
+}
+
+/*******************************************************
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+ ********************************************************/
+int misc_init_r (void)
+{
+	ether_init(); /* better done here so timers are init'ed */
+	return(0);
+}
+
+/****************************************
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ *****************************************/
+void watchdog_init(void)
+{
+	/* There are 4 watch dogs.  1 secure, and 3 general purpose.
+	* The ROM takes care of the secure one. Of the 3 GP ones,
+	* 1 can reset us directly, the other 2 only generate MPU interrupts.
+	*/
+	__raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
+	wait_for_command_complete(WD2_BASE);
+	__raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);
+
+#if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/
+	__raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR);
+	wait_for_command_complete(WD3_BASE);
+	__raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR);
+
+	__raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR);
+	wait_for_command_complete(WD4_BASE);
+	__raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR);
+#endif
+}
+
+/******************************************************
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ ******************************************************/
+void wait_for_command_complete(unsigned int wd_base)
+{
+	int pending = 1;
+	do {
+		pending = __raw_readl(wd_base+WWPS);
+	} while (pending);
+}
+
+/*******************************************************************
+ * Routine:ether_init
+ * Description: take the Ethernet controller out of reset and wait
+ *		   for the EEPROM load to complete.
+ ******************************************************************/
+void ether_init (void)
+{
+#ifdef CONFIG_DRIVER_LAN91C96
+	int cnt = 20;
+
+	__raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */
+
+	__raw_writew(0x0, LAN_RESET_REGISTER);
+	do {
+		__raw_writew(0x1, LAN_RESET_REGISTER);
+		udelay (100);
+		if (cnt == 0)
+			goto h4reset_err_out;
+		--cnt;
+	} while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
+
+	cnt = 20;
+
+	do {
+		__raw_writew(0x0, LAN_RESET_REGISTER);
+		udelay (100);
+		if (cnt == 0)
+			goto h4reset_err_out;
+		--cnt;
+	} while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
+	udelay (1000);
+
+	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
+	udelay (1000);
+
+	h4reset_err_out:
+	return;
+#endif
+}
+
+/**********************************************
+ * Routine: dram_init
+ * Description: sets uboots idea of sdram size
+ **********************************************/
+int dram_init (void)
+{
+	unsigned int size0=0,size1=0;
+	u32 mtype, btype, rev, cpu;
+	u8 chg_on = 0x5; /* enable charge of back up battery */
+	u8 vmode_on = 0x8C;
+	#define NOT_EARLY 0
+
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /* need this a bit early */
+
+	btype = get_board_type();
+	mtype = get_mem_type();
+	rev = get_cpu_rev();
+	cpu = get_cpu_type();
+
+	display_board_info(btype);
+	if (btype == BOARD_H4_MENELAUS){
+		update_mux(btype,mtype); /* combo part on menelaus */
+		i2c_write(I2C_MENELAUS, 0x20, 1, &chg_on, 1); /*fix POR reset bug */
+		i2c_write(I2C_MENELAUS, 0x2, 1, &vmode_on, 1); /* VCORE change on VMODE */
+	}
+
+	if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
+		do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);	/* init other chip select */
+	}
+	size0 = get_sdr_cs_size(SDRC_CS0_OSET);
+	size1 = get_sdr_cs_size(SDRC_CS1_OSET);
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = size0;
+	if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */
+		gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	else /* ES2 and above can remap at 32MB granularity */
+		gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0;
+	gd->bd->bi_dram[1].size = size1;
+
+	return 0;
+}
+
+/**********************************************************
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers
+ *              specific to the hardware
+ *********************************************************/
+void set_muxconf_regs (void)
+{
+	muxSetupSDRC();
+	muxSetupGPMC();
+	muxSetupUsb0();
+	muxSetupUart3();
+	muxSetupI2C1();
+	muxSetupUART1();
+	muxSetupLCD();
+	muxSetupCamera();
+	muxSetupMMCSD();
+	muxSetupTouchScreen();
+	muxSetupHDQ();
+}
+
+/*****************************************************************
+ * Routine: peripheral_enable
+ * Description: Enable the clks & power for perifs (GPT2, UART1,...)
+ ******************************************************************/
+void peripheral_enable(void)
+{
+	unsigned int v, if_clks=0, func_clks=0;
+
+	/* Enable GP2 timer.*/
+	if_clks |= BIT4;
+	func_clks |= BIT4;
+	v = __raw_readl(CM_CLKSEL2_CORE) | 0x4;	/* Sys_clk input OMAP2420_GPT2 */
+	__raw_writel(v, CM_CLKSEL2_CORE);
+	__raw_writel(0x1, CM_CLKSEL_WKUP);
+
+#ifdef CONFIG_SYS_NS16550
+	/* Enable UART1 clock */
+	func_clks |= BIT21;
+	if_clks |= BIT21;
+#endif
+	v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;	/* Interface clocks on */
+	__raw_writel(v,CM_ICLKEN1_CORE );
+	v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
+	__raw_writel(v, CM_FCLKEN1_CORE);
+	delay(1000);
+
+#ifndef KERNEL_UPDATED
+	{
+#define V1 0xffffffff
+#define V2 0x00000007
+
+		__raw_writel(V1, CM_FCLKEN1_CORE);
+		__raw_writel(V2, CM_FCLKEN2_CORE);
+		__raw_writel(V1, CM_ICLKEN1_CORE);
+		__raw_writel(V1, CM_ICLKEN2_CORE);
+	}
+#endif
+}
+
+/****************************************
+ * Routine: muxSetupUsb0   (ostboot)
+ * Description: Setup usb muxing
+ *****************************************/
+void muxSetupUsb0(void)
+{
+	volatile uint8   *MuxConfigReg;
+	volatile uint32  *otgCtrlReg;
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN;
+	*MuxConfigReg &= (uint8)(~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP;
+	*MuxConfigReg &= (uint8)(~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM;
+	*MuxConfigReg &= (uint8)(~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV;
+	*MuxConfigReg &= (uint8)(~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN;
+	*MuxConfigReg &= (uint8)(~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0;
+	*MuxConfigReg &= (uint8)(~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT;
+	*MuxConfigReg &= (uint8)(~0x1F);
+
+	/* setup for USB VBus detection */
+	otgCtrlReg = (volatile uint32 *)USB_OTG_CTRL;
+	*otgCtrlReg |= 0x00040000; /* bit 18 */
+}
+
+/****************************************
+ * Routine: muxSetupUart3   (ostboot)
+ * Description: Setup uart3 muxing
+ *****************************************/
+void muxSetupUart3(void)
+{
+	volatile uint8 *MuxConfigReg;
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_TX_IRTX;
+	*MuxConfigReg &= (uint8)(~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_RX_IRRX;
+	*MuxConfigReg &= (uint8)(~0x1F);
+}
+
+/****************************************
+ * Routine: muxSetupI2C1   (ostboot)
+ * Description: Setup i2c muxing
+ *****************************************/
+void muxSetupI2C1(void)
+{
+	volatile unsigned char  *MuxConfigReg;
+
+	/* I2C1 Clock pin configuration, PIN = M19 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SCL;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* I2C1 Data pin configuration, PIN = L15 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SDA;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* Pull-up required on data line */
+	/* external pull-up already present. */
+	/* *MuxConfigReg |= 0x18 ;*/ /* Mode = 0, PullTypeSel=PU, PullUDEnable=Enabled */
+}
+
+/****************************************
+ * Routine: muxSetupUART1  (ostboot)
+ * Description: Set up uart1 muxing
+ *****************************************/
+void muxSetupUART1(void)
+{
+	volatile unsigned char  *MuxConfigReg;
+
+	/* UART1_CTS pin configuration, PIN = D21 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* UART1_RTS pin configuration, PIN = H21 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* UART1_TX pin configuration, PIN = L20 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* UART1_RX pin configuration, PIN = T21 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+}
+
+/****************************************
+ * Routine: muxSetupLCD   (ostboot)
+ * Description: Setup lcd muxing
+ *****************************************/
+void muxSetupLCD(void)
+{
+	volatile unsigned char  *MuxConfigReg;
+
+	/* LCD_D0 pin configuration, PIN = Y7  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D1 pin configuration, PIN = P10 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D2 pin configuration, PIN = V8  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D3 pin configuration, PIN = Y8  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D4 pin configuration, PIN = W8  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D5 pin configuration, PIN = R10 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D6 pin configuration, PIN = Y9  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D7 pin configuration, PIN = V9  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D8 pin configuration, PIN = W9  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D9 pin configuration, PIN = P11 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D10 pin configuration, PIN = V10 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D11 pin configuration, PIN = Y10 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D12 pin configuration, PIN = W10 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D13 pin configuration, PIN = R11 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D14 pin configuration, PIN = V11 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D15 pin configuration, PIN = W11 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D16 pin configuration, PIN = P12 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D17 pin configuration, PIN = R12 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_PCLK pin configuration,   PIN = W6   */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_VSYNC pin configuration,  PIN = V7  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_HSYNC pin configuration,  PIN = Y6  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_ACBIAS pin configuration, PIN = W7 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+}
+
+/****************************************
+ * Routine: muxSetupCamera  (ostboot)
+ * Description: Setup camera muxing
+ *****************************************/
+void muxSetupCamera(void)
+{
+	volatile unsigned char  *MuxConfigReg;
+
+	/* CAMERA_RSTZ  pin configuration, PIN = Y16 */
+	/* CAM_RST is connected through the I2C IO expander.*/
+	/* MuxConfigReg = (volatile unsigned char *), CONTROL_PADCONF_SYS_NRESWARM*/
+	/* *MuxConfigReg = 0x00 ; / * Mode = 0, PUPD=Disabled   */
+
+	/* CAMERA_XCLK  pin configuration, PIN = U3 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_XCLK;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_LCLK  pin configuration, PIN = V5 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_LCLK;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_VSYNC pin configuration, PIN = U2 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_VS,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_HSYNC pin configuration, PIN = T3 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_HS,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT0 pin configuration, PIN = T4 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D0,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT1 pin configuration, PIN = V2 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D1,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT2 pin configuration, PIN = V3 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D2,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT3 pin configuration, PIN = U4 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D3,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT4 pin configuration, PIN = W2 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D4,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT5 pin configuration, PIN = V4 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D5,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT6 pin configuration, PIN = W3 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D6,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT7 pin configuration, PIN = Y2 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D7,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT8 pin configuration, PIN = Y4 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D8,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT9 pin configuration, PIN = V6 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D9,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+}
+
+/****************************************
+ * Routine: muxSetupMMCSD (ostboot)
+ * Description: set up MMC muxing
+ *****************************************/
+void muxSetupMMCSD(void)
+{
+	volatile unsigned char  *MuxConfigReg;
+
+	/* SDMMC_CLKI pin configuration,  PIN = H15 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SDMMC_CLKO pin configuration,  PIN = G19 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SDMMC_CMD pin configuration,   PIN = H18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
+
+	/* SDMMC_DAT0 pin configuration,  PIN = F20 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
+
+	/* SDMMC_DAT1 pin configuration,  PIN = H14 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
+
+	/* SDMMC_DAT2 pin configuration,  PIN = E19 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
+
+	/* SDMMC_DAT3 pin configuration,  PIN = D19 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
+
+	/* SDMMC_DDIR0 pin configuration, PIN = F19 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SDMMC_DDIR1 pin configuration, PIN = E20 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SDMMC_DDIR2 pin configuration, PIN = F18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SDMMC_DDIR3 pin configuration, PIN = E18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SDMMC_CDIR pin configuration,  PIN = G18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* MMC_CD pin configuration,      PIN = B3  ---2420IP ONLY---*/
+	/* MMC_CD for 2422IP=K1 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A14,
+				   *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
+
+	/* MMC_WP pin configuration,      PIN = B4  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A13,
+				   *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
+}
+
+/******************************************
+ * Routine: muxSetupTouchScreen (ostboot)
+ * Description:  Set up touch screen muxing
+ *******************************************/
+void muxSetupTouchScreen(void)
+{
+	volatile unsigned char  *MuxConfigReg;
+
+	/* SPI1_CLK pin configuration,  PIN = U18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SPI1_MOSI pin configuration, PIN = V20 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SPI1_MISO pin configuration, PIN = T18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SPI1_nCS0 pin configuration, PIN = U19 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* PEN_IRQ pin configuration,   PIN = P20 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MCBSP1_FSR,
+				   *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
+}
+
+/****************************************
+ * Routine: muxSetupHDQ (ostboot)
+ * Description: setup 1wire mux
+ *****************************************/
+void muxSetupHDQ(void)
+{
+	volatile unsigned char  *MuxConfigReg;
+
+	/* HDQ_SIO pin configuration,  PIN = N18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_HDQ_SIO,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+}
+
+/***************************************************************
+ * Routine: muxSetupGPMC (ostboot)
+ * Description: Configures balls which cam up in protected mode
+ ***************************************************************/
+void muxSetupGPMC(void)
+{
+	volatile uint8 *MuxConfigReg;
+	volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C;
+
+	/* gpmc_io_dir */
+	*MCR = 0x19000000;
+
+	/* NOR FLASH CS0 */
+	/* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode - 0; Byte-3	Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3,
+				   *MuxConfigReg = 0x00 ;
+
+	/* signal - Gpmc_iodir; pin - n2; offset - 0x008C; mode - 1; Byte-3	Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3,
+				   *MuxConfigReg = 0x01 ;
+
+	/* MPDB(Multi Port Debug Port) CS1 */
+	/* signal - gpmc_ncs1; pin - N8; offset - 0x008C; mode - 0; Byte-1	Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1,
+				   *MuxConfigReg = 0x00 ;
+
+	/* signal - Gpmc_ncs2; pin - E2; offset - 0x008C; mode - 0; Byte-2	Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2,
+				   *MuxConfigReg = 0x00 ;
+}
+
+/****************************************************************
+ * Routine: muxSetupSDRC  (ostboot)
+ * Description: Configures balls which come up in protected mode
+ ****************************************************************/
+void muxSetupSDRC(void)
+{
+	volatile uint8 *MuxConfigReg;
+
+	/* signal - sdrc_ncs1; pin - C12; offset - 0x00A0; mode - 0; Byte-1	Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE1,
+				   *MuxConfigReg = 0x00 ;
+
+	/* signal - sdrc_a12; pin - D11; offset - 0x0030; mode - 0; Byte-2	Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE2,
+				   *MuxConfigReg = 0x00 ;
+
+	/* signal - sdrc_cke1; pin - B13; offset - 0x00A0; mode - 0; Byte-3	Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE3,
+				   *MuxConfigReg = 0x00;
+
+	if (get_cpu_type() == CPU_2422) {
+		MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE0,
+					   *MuxConfigReg = 0x1b;
+	}
+}
+
+/*****************************************************************************
+ * Routine: update_mux()
+ * Description: Update balls which are different beween boards.  All should be
+ *              updated to match functionaly.  However, I'm only updating ones
+ *              which I'll be using for now.  When power comes into play they
+ *              all need updating.
+ *****************************************************************************/
+void update_mux(u32 btype,u32 mtype)
+{
+	u32 cpu, base = OMAP2420_CTRL_BASE;
+	cpu = get_cpu_type();
+
+	if (btype == BOARD_H4_MENELAUS) {
+		if (cpu == CPU_2420) {
+			/* PIN = B3,  GPIO.0->KBR5,      mode 3,  (pun?),-DO-*/
+			__raw_writeb(0x3, base+0x30);
+			/* PIN = B13, GPIO.38->KBC6,     mode 3,  (pun?)-DO-*/
+			__raw_writeb(0x3, base+0xa3);
+			/* PIN = F1, GPIO.25->HSUSBxx    mode 3,  (for external HS USB)*/
+			/* PIN = H1, GPIO.26->HSUSBxx    mode 3,  (for external HS USB)*/
+			/* PIN = K1, GPMC_ncs6           mode 0,  (on board nand access)*/
+			/* PIN = L2, GPMC_ncs67          mode 0,  (for external HS USB)*/
+			/* PIN = M1 (HSUSBOTG) */
+			/* PIN = P1, GPIO.35->MEN_POK    mode 3,  (menelaus powerok)-DO-*/
+			__raw_writeb(0x3, base+0x9d);
+			/* PIN = U32, (WLAN_CLKREQ) */
+			/* PIN = Y11, WLAN */
+			/* PIN = AA4, GPIO.15->KBC2,     mode 3,  -DO- */
+			__raw_writeb(0x3, base+0xe7);
+			/* PIN = AA8, mDOC */
+			/* PIN = AA10, BT */
+			/* PIN = AA13, WLAN */
+			/* PIN = M18 GPIO.96->MMC2_WP    mode 3   -DO- */
+			__raw_writeb(0x3, base+0x10e);
+			/* PIN = N19 GPIO.98->WLAN_INT   mode 3   -DO- */
+			__raw_writeb(0x3, base+0x110);
+			/* PIN = J15 HHUSB */
+			/* PIN = H19 HSUSB */
+			/* PIN = W13, P13, R13, W16 ... */
+			/* PIN = V12 GPIO.25->I2C_CAMEN  mode 3   -DO- */
+			__raw_writeb(0x3, base+0xde);
+			/* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
+			__raw_writeb(0x0, base+0x12c);
+			/* PIN = AA17->sys_clkreq        mode 0   -DO- */
+			__raw_writeb(0x0, base+0x136);
+		} else if (cpu == CPU_2422) {
+			/* PIN = B3,  GPIO.0->nc,        mode 3,  set above (pun?)*/
+			/* PIN = B13, GPIO.cke1->nc,     mode 0,  set above, (pun?)*/
+			/* PIN = F1, GPIO.25->HSUSBxx    mode 3,  (for external HS USB)*/
+			/* PIN = H1, GPIO.26->HSUSBxx    mode 3,  (for external HS USB)*/
+			/* PIN = K1, GPMC_ncs6           mode 0,  (on board nand access)*/
+			__raw_writeb(0x0, base+0x92);
+			/* PIN = L2, GPMC_ncs67          mode 0,  (for external HS USB)*/
+			/* PIN = M1 (HSUSBOTG) */
+			/* PIN = P1, GPIO.35->MEN_POK    mode 3,  (menelaus powerok)-DO-*/
+			__raw_writeb(0x3, base+0x10c);
+			/* PIN = U32, (WLAN_CLKREQ) */
+			/* PIN = AA4, GPIO.15->KBC2,     mode 3,  -DO- */
+			__raw_writeb(0x3, base+0x30);
+			/* PIN = AA8, mDOC */
+			/* PIN = AA10, BT */
+			/* PIN = AA12, WLAN */
+			/* PIN = M18 GPIO.96->MMC2_WP    mode 3   -DO- */
+			__raw_writeb(0x3, base+0x10e);
+			/* PIN = N19 GPIO.98->WLAN_INT   mode 3   -DO- */
+			__raw_writeb(0x3, base+0x110);
+			/* PIN = J15 HHUSB */
+			/* PIN = H19 HSUSB */
+			/* PIN = W13, P13, R13, W16 ... */
+			/* PIN = V12 GPIO.25->I2C_CAMEN  mode 3   -DO- */
+			__raw_writeb(0x3, base+0xde);
+			/* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
+			__raw_writeb(0x0, base+0x12c);
+			/* PIN = AA17->sys_clkreq        mode 0   -DO- */
+			__raw_writeb(0x0, base+0x136);
+		}
+
+	} else if (btype == BOARD_H4_SDP) {
+		if (cpu == CPU_2420) {
+			/* PIN = B3,  GPIO.0->nc         mode 3,  set above (pun?)*/
+			/* PIN = B13, GPIO.cke1->nc,     mode 0,  set above, (pun?)*/
+			/* Pin = Y11 VLNQ */
+			/* Pin = AA4 VLNQ */
+			/* Pin = AA6 VLNQ */
+			/* Pin = AA8 VLNQ */
+			/* Pin = AA10 VLNQ */
+			/* Pin = AA12 VLNQ */
+			/* PIN = M18 GPIO.96->KBR5       mode 3   -DO- */
+			__raw_writeb(0x3, base+0x10e);
+			/* PIN = N19 GPIO.98->KBC6       mode 3   -DO- */
+			__raw_writeb(0x3, base+0x110);
+			/* PIN = J15 MDOC_nDMAREQ */
+			/* PIN = H19 GPIO.100->KBC2      mode 3   -DO- */
+			__raw_writeb(0x3, base+0x114);
+			/* PIN = W13, V12, P13, R13, W19, W16 ... */
+			/* PIN = AA17 sys_clkreq->bt_clk_req  mode 0  */
+		} else if (cpu == CPU_2422) {
+			/* PIN = B3,  GPIO.0->MMC_CD,    mode 3,  set above */
+			/* PIN = B13, GPIO.38->wlan_int, mode 3,  (pun?)*/
+			/* Pin = Y11 VLNQ */
+			/* Pin = AA4 VLNQ */
+			/* Pin = AA6 VLNQ */
+			/* Pin = AA8 VLNQ */
+			/* Pin = AA10 VLNQ */
+			/* Pin = AA12 VLNQ */
+			/* PIN = M18 GPIO.96->KBR5       mode 3   -DO- */
+			__raw_writeb(0x3, base+0x10e);
+			/* PIN = N19 GPIO.98->KBC6       mode 3   -DO- */
+			__raw_writeb(0x3, base+0x110);
+			/* PIN = J15 MDOC_nDMAREQ */
+			/* PIN = H19 GPIO.100->KBC2      mode 3   -DO- */
+			__raw_writeb(0x3, base+0x114);
+			/* PIN = W13, V12, P13, R13, W19, W16 ... */
+			/* PIN = AA17 sys_clkreq->bt_clk_req  mode 0 */
+		}
+	}
+}
diff --git a/board/ti/omap2420h4/sys_info.c b/board/ti/omap2420h4/sys_info.c
new file mode 100644
index 0000000000..a9f72412a7
--- /dev/null
+++ b/board/ti/omap2420h4/sys_info.c
@@ -0,0 +1,387 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/omap2420.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mem.h>  /* get mem tables */
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <i2c.h>
+
+/**************************************************************************
+ * get_prod_id() - get id info from chips
+ ***************************************************************************/
+static u32 get_prod_id(void)
+{
+	u32 p;
+	p = __raw_readl(PRODUCTION_ID); /* get production ID */
+	return((p & CPU_242X_PID_MASK) >> 16);
+}
+
+/**************************************************************************
+ * get_cpu_type() - low level get cpu type
+ * - no C globals yet.
+ * - just looking to say if this is a 2422 or 2420 or ...
+ * - to start with we will look at switch settings..
+ * - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics
+ *   (mux for 2420, non-mux for 2422).
+ ***************************************************************************/
+u32 get_cpu_type(void)
+{
+	u32 v;
+
+	switch(get_prod_id()){
+		case 1:;/* 2420 */
+		case 2: return(CPU_2420); break; /* 2420 pop */
+		case 4: return(CPU_2422); break;
+		case 8: return(CPU_2423); break;
+		default: break;  /* early 2420/2422's unmarked */
+	}
+
+	v = __raw_readl(TAP_IDCODE_REG);
+	v &= CPU_24XX_ID_MASK;
+	if (v == CPU_2420_CHIPID) {	  /* currently 2420 and 2422 have same id */
+		if (is_gpmc_muxed() == GPMC_MUXED)	  /* if mux'ed */
+			return(CPU_2420);
+		else
+			return(CPU_2422);
+	} else
+		return(CPU_2420); /* don't know, say 2420 */
+}
+
+/******************************************
+ * get_cpu_rev(void) - extract version info
+ ******************************************/
+u32 get_cpu_rev(void)
+{
+	u32 v;
+	v = __raw_readl(TAP_IDCODE_REG);
+	v = v >> 28;
+	return(v+1);  /* currently 2422 and 2420 match up */
+}
+/****************************************************
+ * is_mem_sdr() - return 1 if mem type in use is SDR
+ ****************************************************/
+u32 is_mem_sdr(void)
+{
+	volatile u32 *burst = (volatile u32 *)(SDRC_MR_0+SDRC_CS0_OSET);
+	if(*burst == H4_2420_SDRC_MR_0_SDR)
+		return(1);
+	return(0);
+}
+
+/***********************************************************
+ * get_mem_type() - identify type of mDDR part used.
+ * 2422 uses stacked DDR, 2 parts CS0/CS1.
+ * 2420 may have 1 or 2, no good way to know...only init 1...
+ * when eeprom data is up we can select 1 more.
+ *************************************************************/
+u32 get_mem_type(void)
+{
+	u32 cpu, sdr = is_mem_sdr();
+
+	cpu = get_cpu_type();
+	if (cpu == CPU_2422 || cpu == CPU_2423)
+		return(DDR_STACKED);
+
+	if(get_prod_id() == 0x2)
+		return(XDR_POP);
+
+	if (get_board_type() == BOARD_H4_MENELAUS)
+		if(sdr)
+			return(SDR_DISCRETE);
+		else
+			return(DDR_COMBO);
+	else
+		if(sdr) /* SDP + SDR kit */
+			return(SDR_DISCRETE);
+		else
+			return(DDR_DISCRETE); /* origional SDP */
+}
+
+/***********************************************************************
+ * get_cs0_size() - get size of chip select 0/1
+ ************************************************************************/
+u32 get_sdr_cs_size(u32 offset)
+{
+	u32 size;
+	size = __raw_readl(SDRC_MCFG_0+offset) >> 8; /* get ram size field */
+	size &= 0x2FF;   /* remove unwanted bits */
+	size *= SZ_2M;   /* find size in MB */
+	return(size);
+}
+
+/***********************************************************************
+ * get_board_type() - get board type based on current production stats.
+ *  --- NOTE: 2 I2C EEPROMs will someday be populated with proper info.
+ *      when they are available we can get info from there.  This should
+ *      be correct of all known boards up until today.
+ ************************************************************************/
+u32 get_board_type(void)
+{
+	if (i2c_probe(I2C_MENELAUS) == 0)
+		return(BOARD_H4_MENELAUS);
+	else
+		return(BOARD_H4_SDP);
+}
+
+/******************************************************************
+ * get_sysboot_value() - get init word settings (dip switch on h4)
+ ******************************************************************/
+inline u32 get_sysboot_value(void)
+{
+	return(0x00000FFF & __raw_readl(CONTROL_STATUS));
+}
+
+/***************************************************************************
+ *  get_gpmc0_base() - Return current address hardware will be
+ *     fetching from. The below effectively gives what is correct, its a bit
+ *   mis-leading compared to the TRM.  For the most general case the mask
+ *   needs to be also taken into account this does work in practice.
+ *   - for u-boot we currently map:
+ *       -- 0 to nothing,
+ *       -- 4 to flash
+ *       -- 8 to enent
+ *       -- c to wifi
+ ****************************************************************************/
+u32 get_gpmc0_base(void)
+{
+	u32 b;
+
+	b = __raw_readl(GPMC_CONFIG7_0);
+	b &= 0x1F;	 /* keep base [5:0] */
+	b = b << 24; /* ret 0x0b000000 */
+	return(b);
+}
+
+/*****************************************************************
+ *  is_gpmc_muxed() - tells if address/data lines are multiplexed
+ *****************************************************************/
+u32 is_gpmc_muxed(void)
+{
+	u32 mux;
+	mux = get_sysboot_value();
+	if ((mux & (BIT0 | BIT1 | BIT2 | BIT3)) == (BIT0 | BIT2 | BIT3))
+		return(GPMC_MUXED); /* NAND Boot mode */
+	if (mux & BIT1)	   /* if mux'ed */
+		return(GPMC_MUXED);
+	else
+		return(GPMC_NONMUXED);
+}
+
+/************************************************************************
+ *  get_gpmc0_type() - read sysboot lines to see type of memory attached
+ ************************************************************************/
+u32 get_gpmc0_type(void)
+{
+	u32 type;
+	type = get_sysboot_value();
+	if ((type & (BIT3|BIT2)) == (BIT3|BIT2))
+		return(TYPE_NAND);
+	else
+		return(TYPE_NOR);
+}
+
+/*******************************************************************
+ * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
+ *******************************************************************/
+u32 get_gpmc0_width(void)
+{
+	u32 width;
+	width = get_sysboot_value();
+	if ((width & 0xF) == (BIT3|BIT2))
+		return(WIDTH_8BIT);
+	else
+		return(WIDTH_16BIT);
+}
+
+/*********************************************************************
+ * wait_on_value() - common routine to allow waiting for changes in
+ *   volatile regs.
+ *********************************************************************/
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
+{
+	u32 i = 0, val;
+	do {
+		++i;
+		val = __raw_readl(read_addr) & read_bit_mask;
+		if (val == match_value)
+			return(1);
+		if (i==bound)
+			return(0);
+	} while (1);
+}
+
+/*********************************************************************
+ *  display_board_info() - print banner with board info.
+ *********************************************************************/
+void display_board_info(u32 btype)
+{
+	char cpu_2420[] = "2420";   /* cpu type */
+	char cpu_2422[] = "2422";
+	char cpu_2423[] = "2423";
+	char db_men[] = "Menelaus"; /* board type */
+	char db_ip[] = "IP";
+	char mem_sdr[] = "mSDR";    /* memory type */
+	char mem_ddr[] = "mDDR";
+	char t_tst[] = "TST";	    /* security level */
+	char t_emu[] = "EMU";
+	char t_hs[] = "HS";
+	char t_gp[] = "GP";
+	char unk[] = "?";
+
+	char *cpu_s, *db_s, *mem_s, *sec_s;
+	u32 cpu, rev, sec;
+
+	rev = get_cpu_rev();
+	cpu = get_cpu_type();
+	sec = get_device_type();
+
+	if(is_mem_sdr())
+		mem_s = mem_sdr;
+	else
+		mem_s = mem_ddr;
+
+	if(cpu == CPU_2423)
+		cpu_s = cpu_2423;
+	else if (cpu == CPU_2422)
+		cpu_s = cpu_2422;
+	else
+		cpu_s = cpu_2420;
+
+	if(btype ==  BOARD_H4_MENELAUS)
+		db_s = db_men;
+	else
+		db_s = db_ip;
+
+	switch(sec){
+		case TST_DEVICE: sec_s = t_tst; break;
+		case EMU_DEVICE: sec_s = t_emu; break;
+		case HS_DEVICE:  sec_s = t_hs; break;
+		case GP_DEVICE:  sec_s = t_gp; break;
+		default: sec_s = unk;
+	}
+
+	printf("OMAP%s-%s revision %d\n", cpu_s, sec_s, rev-1);
+	printf("TI H4 SDP Base Board + %s Daughter Board + %s \n", db_s, mem_s);
+}
+
+/*************************************************************************
+ * get_board_rev() - setup to pass kernel board revision information
+ *          0 = 242x IP platform (first 2xx boards)
+ *          1 = 242x Menelaus platfrom.
+ *************************************************************************/
+u32 get_board_rev(void)
+{
+	u32 rev = 0;
+	u32 btype = get_board_type();
+
+	if (btype == BOARD_H4_MENELAUS){
+		rev = 1;
+	}
+	return(rev);
+}
+
+/********************************************************
+ *  get_base(); get upper addr of current execution
+ *******************************************************/
+u32 get_base(void)
+{
+	u32  val;
+	__asm__ __volatile__("mov %0, pc \n" : "=r" (val) : : "memory");
+	val &= 0xF0000000;
+	val >>= 28;
+	return(val);
+}
+
+/********************************************************
+ *  get_base2(); get 2upper addr of current execution
+ *******************************************************/
+u32 get_base2(void)
+{
+	u32  val;
+	__asm__ __volatile__("mov %0, pc \n" : "=r" (val) : : "memory");
+	val &= 0xFF000000;
+	val >>= 24;
+	return(val);
+}
+
+/********************************************************
+ *  running_in_flash() - tell if currently running in
+ *   flash.
+ *******************************************************/
+u32 running_in_flash(void)
+{
+	if (get_base() < 4)
+		return(1);  /* in flash */
+	return(0); /* running in SRAM or SDRAM */
+}
+
+/********************************************************
+ *  running_in_sram() - tell if currently running in
+ *   sram.
+ *******************************************************/
+u32 running_in_sram(void)
+{
+	if (get_base() == 4)
+		return(1);  /* in SRAM */
+	return(0); /* running in FLASH or SDRAM */
+}
+/********************************************************
+ *  running_in_sdram() - tell if currently running in
+ *   flash.
+ *******************************************************/
+u32 running_in_sdram(void)
+{
+	if (get_base() > 4)
+		return(1);  /* in sdram */
+	return(0); /* running in SRAM or FLASH */
+}
+
+/*************************************************************
+ *  running_from_internal_boot() - am I a signed NOR image.
+ *************************************************************/
+u32 running_from_internal_boot(void)
+{
+	u32 v, base;
+
+	v = get_sysboot_value() & BIT3;
+	base = get_base2();
+	/* if running at mask rom flash address and
+	 * sysboot3 says this was an internal boot
+	 */
+	if ((base == 0x08) && v)
+		return(1);
+	else
+		return(0);
+}
+
+/*************************************************************
+ *  get_device_type(): tell if GP/HS/EMU/TST
+ *************************************************************/
+u32 get_device_type(void)
+{
+	int mode;
+	mode = __raw_readl(CONTROL_STATUS) & (BIT10|BIT9|BIT8);
+	return(mode >>= 8);
+}
diff --git a/board/ti/omap5912osk/Makefile b/board/ti/omap5912osk/Makefile
new file mode 100644
index 0000000000..e9bb0ecd72
--- /dev/null
+++ b/board/ti/omap5912osk/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= omap5912osk.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ti/omap5912osk/config.mk b/board/ti/omap5912osk/config.mk
new file mode 100644
index 0000000000..5362a4f424
--- /dev/null
+++ b/board/ti/omap5912osk/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2002-2004
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Kshitij Gupta <Kshitij@ti.com>
+#
+# (C) Copyright 2004
+# Texas Instruments, <www.ti.com>
+# Rishi Bhattacharya <rishi@ti.com>
+#
+# TI OSK board with OMAP5912 (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# OSK has 1 bank of 256 MB SDRAM
+# Physical Address:
+# 1000'0000 to 2000'0000
+#
+#
+# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
+# (mem base + reserved)
+#
+# we load ourself to 1108'0000
+#
+#
+
+
+TEXT_BASE = 0x11080000
diff --git a/board/ti/omap5912osk/lowlevel_init.S b/board/ti/omap5912osk/lowlevel_init.S
new file mode 100644
index 0000000000..7bfdb26325
--- /dev/null
+++ b/board/ti/omap5912osk/lowlevel_init.S
@@ -0,0 +1,477 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
+ *
+ * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1610)
+#include <./configs/omap1510.h>
+#endif
+
+
+_TEXT_BASE:
+	.word	TEXT_BASE	/* sdram load addr from config.mk */
+
+.globl lowlevel_init
+lowlevel_init:
+
+	/*------------------------------------------------------*
+	 * Ensure i-cache is enabled                            *
+	 * To configure TC regs without fetching instruction    *
+	 *------------------------------------------------------*/
+	mrc	p15, 0, r0, c1, c0
+	orr	r0, r0, #0x1000
+	mcr	p15, 0, r0, c1, c0
+
+	/*------------------------------------------------------*
+	 *mask all IRQs by setting all bits in the INTMR default*
+	 *------------------------------------------------------*/
+	mov	r1, #0xffffffff
+	ldr	r0, =REG_IHL1_MIR
+	str	r1, [r0]
+	ldr	r0, =REG_IHL2_MIR
+	str	r1, [r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT1)                   *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT1
+	ldr	r1,	VAL_ARM_IDLECT1
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT2)                   *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT2
+	ldr	r1,	VAL_ARM_IDLECT2
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT3)                   *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT3
+	ldr	r1,	VAL_ARM_IDLECT3
+	str	r1,	[r0]
+
+	mov	r1,	#0x01               /* PER_EN bit */
+	ldr	r0,	REG_ARM_RSTCT2
+	strh	r1,	[r0]            /* CLKM; Peripheral reset. */
+
+	/* Set CLKM to Sync-Scalable */
+	mov	r1,	#0x1000
+	ldr	r0,	REG_ARM_SYSST
+
+	mov	r2,	#0
+1:	cmp	r2,	#1
+	streqh	r1,	[r0]
+	add	r2,	r2,	#1
+	cmp	r2,	#0x100              /* wait for any bubbles to finish */
+	bne	1b
+
+	ldr	r1,	VAL_ARM_CKCTL
+	ldr	r0,	REG_ARM_CKCTL
+	strh	r1,	[r0]
+
+	/* a few nops to let settle */
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	/* setup DPLL 1 */
+	/* Ramp up the clock to 96Mhz */
+	ldr	r1,	VAL_DPLL1_CTL
+	ldr	r0,	REG_DPLL1_CTL
+	strh	r1,	[r0]
+	ands	r1,	r1,	#0x10       /* Check if PLL is enabled. */
+	beq	lock_end                /* Do not look for lock if BYPASS selected */
+2:
+	ldrh	r1,	[r0]
+	ands	r1,	r1,	#0x01       /* Check the LOCK bit.*/
+	beq 2b                      /* loop until bit goes hi. */
+lock_end:
+
+	/*------------------------------------------------------*
+	 * Turn off the watchdog during init...                 *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_WATCHDOG
+	ldr	r1,	WATCHDOG_VAL1
+	str	r1,	[r0]
+	ldr	r1,	WATCHDOG_VAL2
+	str	r1,	[r0]
+	ldr	r0,	REG_WSPRDOG
+	ldr	r1,	WSPRDOG_VAL1
+	str	r1,	[r0]
+	ldr	r0,	REG_WWPSDOG
+
+watch1Wait:
+	ldr	r1,	[r0]
+	tst	r1,	#0x10
+	bne	watch1Wait
+
+	ldr	r0,	REG_WSPRDOG
+	ldr	r1,	WSPRDOG_VAL2
+	str	r1,	[r0]
+	ldr	r0,	REG_WWPSDOG
+watch2Wait:
+	ldr	r1,	[r0]
+	tst	r1,	#0x10
+	bne	watch2Wait
+
+	/* Set memory timings corresponding to the new clock speed */
+	ldr	r3, VAL_SDRAM_CONFIG_SDF0
+
+	/* Check execution location to determine current execution location
+	 * and branch to appropriate initialization code.
+	 */
+	mov	r0,	#0x10000000         /* Load physical SDRAM base. */
+	mov	r1,	pc                  /* Get current execution location. */
+	cmp	r1,	r0                  /* Compare. */
+	bge	skip_sdram              /* Skip over EMIF-fast initialization if running from SDRAM. */
+
+	/* identify the device revision, -- TMX or TMP(TMS) */
+	ldr	r0, REG_DEVICE_ID
+	ldr	r1, [r0]
+
+	ldr	r0, VAL_DEVICE_ID_TMP
+	mov	r1, r1, lsl #15
+	mov	r1, r1, lsr #16
+	cmp	r0, r1
+	bne	skip_TMP_Patch
+
+	/* Enable TMP/TMS device new features */
+	mov	r0, #1
+	ldr	r1, REG_TC_EMIFF_DOUBLER
+	str	r0, [r1]
+
+	/* Enable new ac parameters */
+	mov	r0, #0x0b
+	ldr	r1, REG_SDRAM_CONFIG2
+	str	r0, [r1]
+
+	ldr	r3, VAL_SDRAM_CONFIG_SDF1
+
+skip_TMP_Patch:
+
+	/*
+	* Delay for SDRAM initialization.
+	*/
+	mov	r0,	#0x1800		/* value should be checked */
+3:
+	subs	r0,	r0,	#0x1	/* Decrement count */
+	bne	3b
+
+	/*
+	 * Set SDRAM control values. Disable refresh before MRS command.
+	 */
+
+	/* mobile ddr operation */
+	ldr	r0,	REG_SDRAM_OPERATION
+	mov	r2,	#07
+	str	r2,	[r0]
+
+	/* config register */
+	ldr	r0,	REG_SDRAM_CONFIG
+	str	r3,	[r0]
+
+	/* manual command register */
+	ldr	r0,	REG_SDRAM_MANUAL_CMD
+
+	/* issue set cke high */
+	mov	r1,	#CMD_SDRAM_CKE_SET_HIGH
+	str	r1,	[r0]
+
+	/* issue nop */
+	mov	r1,	#CMD_SDRAM_NOP
+	str	r1,	[r0]
+
+	mov	r2,	#0x0100
+waitMDDR1:
+	subs	r2,	r2,	 #1
+	bne	waitMDDR1	/* delay loop */
+
+	/* issue precharge */
+	mov	r1,	#CMD_SDRAM_PRECHARGE
+	str	r1,	[r0]
+
+	/* issue autorefresh x 2 */
+	mov	r1,	#CMD_SDRAM_AUTOREFRESH
+	str	r1,	[r0]
+	str	r1,	[r0]
+
+	/* mrs register ddr mobile */
+	ldr	r0,	REG_SDRAM_MRS
+	mov	r1,	#0x33
+	str	r1,	[r0]
+
+	/* emrs1 low-power register */
+	ldr	r0,	REG_SDRAM_EMRS1
+	/* self refresh on all banks */
+	mov	r1,	#0
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_URD_CONTROL
+	ldr	r1,	DLL_URD_CONTROL_VAL
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_LRD_CONTROL
+	ldr	r1,	DLL_LRD_CONTROL_VAL
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_WRT_CONTROL
+	ldr	r1,	DLL_WRT_CONTROL_VAL
+	str	r1,	[r0]
+
+	/* delay loop */
+	mov	r0,	#0x0100
+waitMDDR2:
+	subs	r0,	r0,	#1
+	bne	waitMDDR2
+
+	/*
+	 * Delay for SDRAM initialization.
+	 */
+	mov	r0,	#0x1800
+4:
+	subs	r0,	r0,	#1	/* Decrement count. */
+	bne	4b
+	b	common_tc
+
+skip_sdram:
+	ldr	r0,	REG_SDRAM_CONFIG
+	str	r3,	[r0]
+
+common_tc:
+	/* slow interface */
+	ldr	r1,	VAL_TC_EMIFS_CS0_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS0_CONFIG
+	str	r1,	[r0] /* Chip Select 0 */
+
+	ldr	r1,	VAL_TC_EMIFS_CS1_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS1_CONFIG
+	str	r1,	[r0] /* Chip Select 1 */
+
+	ldr	r1,	VAL_TC_EMIFS_CS3_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS3_CONFIG
+	str	r1,	[r0] /* Chip Select 3 */
+
+	ldr	r1,	VAL_TC_EMIFS_DWS
+	ldr	r0,	REG_TC_EMIFS_DWS
+	str	r1,	[r0] /* Enable EMIFS.RDY for CS1 (ether) */
+
+#ifdef CONFIG_H2_OMAP1610
+	/* inserting additional 2 clock cycle hold time for LAN */
+	ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
+	ldr	r1,     VAL_TC_EMIFS_CS1_ADVANCED
+	str     r1,     [r0]
+#endif
+	/* Start MPU Timer 1 */
+	ldr	r0,	REG_MPU_LOAD_TIMER
+	ldr	r1,	VAL_MPU_LOAD_TIMER
+	str	r1,	[r0]
+
+	ldr	r0,	REG_MPU_CNTL_TIMER
+	ldr	r1,	VAL_MPU_CNTL_TIMER
+	str	r1,	[r0]
+
+	/* back to arch calling code */
+	mov	pc,	lr
+
+	/* the literal pools origin */
+	.ltorg
+
+REG_DEVICE_ID:			/* 32 bits */
+	.word 0xfffe2004
+REG_TC_EMIFS_CONFIG:
+	.word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
+	.word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
+	.word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
+	.word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
+	.word 0xfffecc1c
+REG_TC_EMIFS_DWS:		/* 32 bits */
+	.word 0xfffecc40
+#ifdef CONFIG_H2_OMAP1610
+REG_TC_EMIFS_CS1_ADVANCED:	/* 32 bits */
+	.word 0xfffecc54
+#endif
+
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL:			/* 16 bits */
+	.word 0xfffece00
+REG_ARM_IDLECT3:		/* 16 bits */
+	.word 0xfffece24
+REG_ARM_IDLECT2:		/* 16 bits */
+	.word 0xfffece08
+REG_ARM_IDLECT1:		/* 16 bits */
+	.word 0xfffece04
+REG_ARM_RSTCT2:			/* 16 bits */
+	.word 0xfffece14
+REG_ARM_SYSST:			/* 16 bits */
+	.word 0xfffece18
+
+/* DPLL control registers */
+REG_DPLL1_CTL:			/* 16 bits */
+	.word 0xfffecf00
+
+/* Watch Dog register */
+/* secure watchdog stop */
+REG_WSPRDOG:
+	.word 0xfffeb048
+/* watchdog write pending */
+REG_WWPSDOG:
+	.word 0xfffeb034
+
+WSPRDOG_VAL1:
+	.word 0x0000aaaa
+WSPRDOG_VAL2:
+	.word 0x00005555
+
+/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
+ counter @8192 rows, 10 ns, 8 burst */
+REG_SDRAM_CONFIG:
+	.word 0xfffecc20
+REG_SDRAM_CONFIG2:
+	.word 0xfffecc3c
+REG_TC_EMIFF_DOUBLER:		/* 32 bits */
+	.word 0xfffecc60
+
+/* Operation register */
+REG_SDRAM_OPERATION:
+	.word 0xfffecc80
+
+/* Manual command register */
+REG_SDRAM_MANUAL_CMD:
+	.word 0xfffecc84
+
+/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
+REG_SDRAM_MRS:
+	.word 0xfffecc70
+
+/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
+REG_SDRAM_EMRS1:
+	.word 0xfffecc78
+
+/* WRT DLL register */
+REG_DLL_WRT_CONTROL:
+	.word 0xfffecc68
+DLL_WRT_CONTROL_VAL:
+	.word 0x03f00002    /* Phase of 72deg, write offset +31  */
+
+/* URD DLL register */
+REG_DLL_URD_CONTROL:
+	.word 0xfffeccc0
+DLL_URD_CONTROL_VAL:
+	.word 0x00800002    /* Phase of 72deg, read offset +31  */
+
+/* LRD DLL register */
+REG_DLL_LRD_CONTROL:
+	.word 0xfffecccc
+DLL_LRD_CONTROL_VAL:
+	.word 0x00800002    /* read offset +31  */
+
+REG_WATCHDOG:
+	.word 0xfffec808
+WATCHDOG_VAL1:
+	.word 0x000000f5
+WATCHDOG_VAL2:
+	.word 0x000000a0
+
+REG_MPU_LOAD_TIMER:
+	.word 0xfffec504
+REG_MPU_CNTL_TIMER:
+	.word 0xfffec500
+VAL_MPU_LOAD_TIMER:
+	.word 0xffffffff
+VAL_MPU_CNTL_TIMER:
+	.word 0xffffffa1
+
+/* 96 MHz Samsung Mobile DDR */
+/* Original setting for TMX device */
+VAL_SDRAM_CONFIG_SDF0:
+    .word 0x0014e6fe
+
+/* NEW_SYS_FREQ mode (valid only TMP/TMS devices) */
+VAL_SDRAM_CONFIG_SDF1:
+    .word 0x0114e6fe
+
+VAL_ARM_CKCTL:
+	.word 0x2000		/* was:	0x3000, now use CLK_REF for timer input */
+VAL_DPLL1_CTL:
+	.word 0x2830
+
+#ifdef CONFIG_OSK_OMAP5912
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x002130b0
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x00001133
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0x000055f0
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x88013141
+VAL_TC_EMIFS_DWS:	/* Enable EMIFS.RDY for CS1 access (ether) */
+	.word 0x000000c0
+VAL_DEVICE_ID_TMP:	/* TMP/TMS=0xb65f, TMX=0xb58c */
+	.word 0xb65f
+#endif
+
+#ifdef CONFIG_H2_OMAP1610
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x00203331
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x8180fff3
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0xf800f22a
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x88013141
+VAL_TC_EMIFS_CS1_ADVANCED:
+	.word 0x00000022
+#endif
+
+VAL_ARM_IDLECT1:
+	.word 0x00000400
+VAL_ARM_IDLECT2:
+	.word 0x00000886
+VAL_ARM_IDLECT3:
+	.word 0x00000015
+
+/* command values */
+.equ CMD_SDRAM_NOP,             0x00000000
+.equ CMD_SDRAM_PRECHARGE,       0x00000001
+.equ CMD_SDRAM_AUTOREFRESH,     0x00000002
+.equ CMD_SDRAM_CKE_SET_HIGH,    0x00000007
diff --git a/board/ti/omap5912osk/omap5912osk.c b/board/ti/omap5912osk/omap5912osk.c
new file mode 100644
index 0000000000..6993b136ee
--- /dev/null
+++ b/board/ti/omap5912osk/omap5912osk.c
@@ -0,0 +1,308 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Rishi Bhattacharya <rishi@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_OMAP1610)
+#include <./configs/omap1510.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void flash__init (void);
+void ether__init (void);
+void set_muxconf_regs (void);
+void peripheral_power_enable (void);
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP_OSK;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+	/* Configure MUX settings */
+	set_muxconf_regs ();
+	peripheral_power_enable ();
+
+/* this speeds up your boot a quite a bit.  However to make it
+ *  work, you need make sure your kernel startup flush bug is fixed.
+ *  ... rkw ...
+ */
+	icache_enable ();
+
+	flash__init ();
+	ether__init ();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	/* currently empty */
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+void flash__init (void)
+{
+#define EMIFS_GlB_Config_REG 0xfffecc0c
+	unsigned int regval;
+	regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
+	/* Turn off write protection for flash devices. */
+	regval = regval | 0x0001;
+	*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
+}
+/*************************************************************
+ Routine:ether__init
+ Description: take the Ethernet controller out of reset and wait
+			   for the EEPROM load to complete.
+*************************************************************/
+void ether__init (void)
+{
+#define ETH_CONTROL_REG 0x0480000b
+	int i;
+
+	*((volatile unsigned short *) 0xfffece08) = 0x03FF;
+	*((volatile unsigned short *) 0xfffb3824) = 0x8000;
+	*((volatile unsigned short *) 0xfffb3830) = 0x0000;
+	*((volatile unsigned short *) 0xfffb3834) = 0x0009;
+	*((volatile unsigned short *) 0xfffb3838) = 0x0009;
+	*((volatile unsigned short *) 0xfffb3818) = 0x0002;
+	*((volatile unsigned short *) 0xfffb382C) = 0x0048;
+	*((volatile unsigned short *) 0xfffb3824) = 0x8603;
+	udelay (3);
+	for (i=0;i<2000;i++);
+	*((volatile unsigned short *) 0xfffb381C) = 0x6610;
+	udelay (30);
+	for (i=0;i<10000;i++);
+
+	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
+	udelay (3);
+
+
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+/******************************************************
+ Routine: set_muxconf_regs
+ Description: Setting up the configuration Mux registers
+			  specific to the hardware
+*******************************************************/
+void set_muxconf_regs (void)
+{
+	volatile unsigned int *MuxConfReg;
+	/* set each registers to its reset value; */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
+	/* setup for UART1 */
+	*MuxConfReg &= ~(0x02000000);	/* bit 25 */
+	/* setup for UART2 */
+	*MuxConfReg &= ~(0x01000000);	/* bit 24 */
+	/* Disable Uwire CS Hi-Z */
+	*MuxConfReg |= 0x08000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6);
+	/*setup mux for UART3 */
+	*MuxConfReg |= 0x00000001;	/* bit3, 1, 0 (mux0 5,5,26) */
+	*MuxConfReg &= ~0x0000003e;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8);
+	/* Disable Uwire CS Hi-Z */
+	*MuxConfReg |= 0x00001200;	/*bit 9 for CS0 12 for CS3 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9);
+	/*  Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the  */
+	/*  hardware will actually use TX and RTS based on bit 25 in  */
+	/*  FUNC_MUX_CTRL_0.  I told you this thing was screwy!	 */
+	*MuxConfReg |= 0x00201000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C);
+	/* setup for UART2 */
+	/*  Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the  */
+	/*  hardware will actually use TX and RTS based on bit 24 in  */
+	/*  FUNC_MUX_CTRL_0. */
+	*MuxConfReg |= 0x09000000;
+	MuxConfReg =
+	(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_D);
+	*MuxConfReg |= 0x00000020;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1);
+	*MuxConfReg = 0x00000000;
+	/* mux setup for SD/MMC driver */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2);
+	*MuxConfReg &= 0xFFFE0FFF;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	/* bit 13 for MMC2 XOR_CLK */
+	*MuxConfReg &= ~(0x00002000);
+	/* bit 29 for UART 1 */
+	*MuxConfReg &= ~(0x00002000);
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
+	/* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */
+	*MuxConfReg |= 0x000C0000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL);
+	*MuxConfReg &= ~(0x00000070);
+	*MuxConfReg &= ~(0x00000008);
+	*MuxConfReg |= 0x00000003;
+	*MuxConfReg |= 0x00000180;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	/* bit 17, software controls VBUS */
+	*MuxConfReg &= ~(0x00020000);
+	/* Enable USB 48 and 12M clocks */
+	*MuxConfReg |= 0x00000200;
+	*MuxConfReg &= ~(0x00000180);
+	/*2.75V for MMCSDIO1 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0);
+	*MuxConfReg = 0x00001FE7;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_0);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_1);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_4);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4);
+	*MuxConfReg = 0x00000000;
+	/* Turn on UART2 48 MHZ clock */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	*MuxConfReg |= 0x40000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) USB_OTG_CTRL);
+	/* setup for USB VBus detection OMAP161x */
+	*MuxConfReg |= 0x00040000;	/* bit 18 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
+	/* PullUps for SD/MMC driver */
+	*MuxConfReg |= ~(0xFFFE0FFF);
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0);
+	*MuxConfReg = COMP_MODE_ENABLE;
+}
+
+/******************************************************
+ Routine: peripheral_power_enable
+ Description: Enable the power for UART1
+*******************************************************/
+void peripheral_power_enable (void)
+{
+#define UART1_48MHZ_ENABLE	((unsigned short)0x0200)
+#define SW_CLOCK_REQUEST	((volatile unsigned short *)0xFFFE0834)
+
+	*SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE;
+}
+
+/*
+ * Check Board Identity
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	puts("Board: OSK5912");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
diff --git a/board/ti/omap730p2/Makefile b/board/ti/omap730p2/Makefile
new file mode 100644
index 0000000000..0d7ae6145c
--- /dev/null
+++ b/board/ti/omap730p2/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= omap730p2.o flash.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ti/omap730p2/config.mk b/board/ti/omap730p2/config.mk
new file mode 100644
index 0000000000..6940320c3a
--- /dev/null
+++ b/board/ti/omap730p2/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Kshitij Gupta <Kshitij@ti.com>
+#
+# TI Perseus 2 board with OMAP720 (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Innovator has 1 bank of 256 MB SDRAM
+# Physical Address:
+# 1000'0000 to 2000'0000
+#
+#
+# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
+# (mem base + reserved)
+#
+# we load ourself to 1108'0000
+#
+#
+
+TEXT_BASE = 0x11080000
diff --git a/board/ti/omap730p2/flash.c b/board/ti/omap730p2/flash.c
new file mode 100644
index 0000000000..5b56b98393
--- /dev/null
+++ b/board/ti/omap730p2/flash.c
@@ -0,0 +1,477 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)			__swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)			__swab32(x)
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef {
+	unsigned int sector_number;
+	unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+OrgDef OrgIntel_28F256L18T[] = {
+	{4, 32 * 1024},				/* 4 * 32kBytes sectors */
+	{255, 128 * 1024},			/* 255 * 128kBytes sectors */
+};
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+unsigned long flash_init (void);
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+void flash_print_info (flash_info_t * info);
+void flash_unprotect_sectors (FPWV * addr);
+int flash_erase (flash_info_t * info, int s_first, int s_last);
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+	OrgDef *pOrgDef;
+
+	pOrgDef = OrgIntel_28F256L18T;
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			if (i > 255) {
+				info->start[i] = base + (i * 0x8000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base +
+						(i * PHYS_FLASH_SECT_SIZE);
+				info->protect[i] = 0;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F256L18T:
+		printf ("FLASH 28F256L18T\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);		/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];	/* device ID        */
+	switch (value) {
+
+	case (FPW) (INTEL_ID_28F256L18T):
+		info->flash_id += FLASH_28F256L18T;
+		info->sector_count = 259;
+		info->size = 0x02000000;
+		break;			/* => 32 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/* unprotects a sector for write and erase
+ * on some intel parts, this unprotects the entire chip, but it
+ * wont hurt to call this additional times per sector...
+ */
+void flash_unprotect_sectors (FPWV * addr)
+{
+#define PD_FINTEL_WSMS_READY_MASK    0x0080
+
+	*addr = (FPW) 0x00500050;	/* clear status register */
+
+	/* this sends the clear lock bit command */
+	*addr = (FPW) 0x00600060;
+	*addr = (FPW) 0x00D000D0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+				info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			flash_unprotect_sectors (addr);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;/* clear status register */
+			*addr = (FPW) 0x00200020;/* erase setup */
+			*addr = (FPW) 0x00D000D0;/* erase confirm */
+
+			while (((status =
+				*addr) & (FPW) 0x00800080) !=
+				(FPW) 0x00800080) {
+					if (get_timer_masked () >
+					CONFIG_SYS_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					/* suspend erase     */
+					*addr = (FPW) 0x00B000B0;
+					/* reset to read mode */
+					*addr = (FPW) 0x00FF00FF;
+					rcode = 1;
+					break;
+				}
+			}
+
+			/* clear status register cmd.   */
+			*addr = (FPW) 0x00500050;
+			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	flash_unprotect_sectors (addr);
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/ti/omap730p2/lowlevel_init.S b/board/ti/omap730p2/lowlevel_init.S
new file mode 100644
index 0000000000..d4e97a5aa7
--- /dev/null
+++ b/board/ti/omap730p2/lowlevel_init.S
@@ -0,0 +1,395 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003-2004
+ *
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
+ *
+ * Modified for OMAP730 P2 Board by Dave Peverley, MPC-Data Limited
+ * (http://www.mpc-data.co.uk)
+ *
+ * TODO : Tidy up and change to use system register defines
+ *        from omap730.h where possible.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP730)
+#include <./configs/omap730.h>
+#endif
+
+_TEXT_BASE:
+	.word	TEXT_BASE	/* sdram load addr from config.mk */
+
+.globl lowlevel_init
+lowlevel_init:
+	/* Save callers address in r11 - r11 must never be modified */
+	mov r11, lr
+
+	/*------------------------------------------------------*
+	 *mask all IRQs by setting all bits in the INTMR default*
+	 *------------------------------------------------------*/
+	mov	r1,	#0xffffffff
+	ldr	r0,	=REG_IHL1_MIR
+	str	r1,	[r0]
+	ldr	r0,	=REG_IHL2_MIR
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT1)                   *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT1
+	ldr	r1,	VAL_ARM_IDLECT1
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT2)		        *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT2
+	ldr	r1,	VAL_ARM_IDLECT2
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT3)		        *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT3
+	ldr	r1,	VAL_ARM_IDLECT3
+	str	r1,	[r0]
+
+
+	mov	r1,	#0x01		/* PER_EN bit */
+	ldr	r0,	REG_ARM_RSTCT2
+	strh	r1,	[r0]		/* CLKM; Peripheral reset. */
+
+	/* Set CLKM to Sync-Scalable	*/
+	/* I supposedly need to enable the dsp clock before switching */
+	mov	r1,	#0x1000
+	ldr	r0,	REG_ARM_SYSST
+	strh	r1,	[r0]
+	mov	r0,	#0x400
+1:
+	subs	r0,	r0,	#0x1	/* wait for any bubbles to finish */
+	bne	1b
+	ldr	r1,	VAL_ARM_CKCTL
+	ldr	r0,	REG_ARM_CKCTL
+	strh	r1,	[r0]
+
+	/* a few nops to let settle */
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	/* setup DPLL 1 */
+	/* Ramp up the clock to 96Mhz */
+	ldr	r1,	VAL_DPLL1_CTL
+	ldr	r0,	REG_DPLL1_CTL
+	strh	r1,	[r0]
+	ands	r1,	r1,	#0x10	/* Check if PLL is enabled. */
+	beq	lock_end	/* Do not look for lock if BYPASS selected */
+2:
+	ldrh	r1,	[r0]
+	ands	r1,	r1,	#0x01	/*	Check the LOCK bit.*/
+	beq 2b			/*	loop until bit goes hi. */
+lock_end:
+
+	/*------------------------------------------------------*
+	 * Turn off the watchdog during init...			*
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_WATCHDOG
+	ldr	r1,	WATCHDOG_VAL1
+	str	r1,	[r0]
+	ldr	r1,	WATCHDOG_VAL2
+	str	r1,	[r0]
+	ldr	r0,	REG_WSPRDOG
+	ldr	r1,	WSPRDOG_VAL1
+	str	r1,	[r0]
+	ldr	r0,	REG_WWPSDOG
+
+watch1Wait:
+	ldr	r1,	[r0]
+	tst	r1,	#0x10
+	bne	watch1Wait
+
+	ldr	r0,	REG_WSPRDOG
+	ldr	r1,	WSPRDOG_VAL2
+	str	r1,	[r0]
+	ldr	r0,	REG_WWPSDOG
+watch2Wait:
+	ldr	r1,	[r0]
+	tst	r1,	#0x10
+	bne	watch2Wait
+
+	/* Set memory timings corresponding to the new clock speed */
+
+	/* Check execution location to determine current execution location
+	 * and branch to appropriate initialization code.
+	 */
+	/* Compare physical SDRAM base & current execution location. */
+	and     r0, pc, #0xF0000000
+	/* Compare. */
+	cmp     r0, #0
+	/* Skip over EMIF-fast initialization if running from SDRAM. */
+	bne	skip_sdram
+
+	/*
+	* Delay for SDRAM initialization.
+	*/
+	mov	r3,	#0x1800		/* value should be checked */
+3:
+	subs	r3,	r3,	#0x1	/* Decrement count */
+	bne	3b
+
+	ldr	r0,	REG_SDRAM_CONFIG
+	ldr	r1,	SDRAM_CONFIG_VAL
+	str	r1,	[r0]
+
+	ldr	r0,	REG_SDRAM_MRS_LEGACY
+	ldr	r1,	SDRAM_MRS_VAL
+	str	r1,	[r0]
+
+skip_sdram:
+
+common_tc:
+	/* slow interface */
+	ldr	r1,	VAL_TC_EMIFS_CS0_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS0_CONFIG
+	str	r1,	[r0] /* Chip Select 0 */
+
+	ldr	r1,	VAL_TC_EMIFS_CS1_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS1_CONFIG
+	str	r1,	[r0] /* Chip Select 1 */
+	ldr	r1,	VAL_TC_EMIFS_CS2_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS2_CONFIG
+	str	r1,	[r0] /* Chip Select 2 */
+	ldr	r1,	VAL_TC_EMIFS_CS3_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS3_CONFIG
+	str	r1,	[r0] /* Chip Select 3 */
+
+	/* 48MHz clock request for UART1 */
+	ldr	r1,	PERSEUS2_CONFIG_BASE
+	ldrh	r0,	[r1, #CONFIG_PCC_CONF]
+	orr	r0,	r0, #CONF_MOD_UART1_CLK_MODE_R
+	strh	r0,	[r1, #CONFIG_PCC_CONF]
+
+	/* Initialize public and private rheas
+	 *  - set access factor 2 on both rhea / strobe
+	 *  - disable write buffer on strb0, enable write buffer on strb1
+	 */
+
+	ldr	R0,	REG_RHEA_PUB_CTL
+	ldr	R1,	REG_RHEA_PRIV_CTL
+	ldr	R2,	VAL_RHEA_CTL
+	strh	R2,	[R0]
+	strh	R2,	[R1]
+	mov	R3,	#2          /* disable write buffer on strb0, enable write buffer on strb1 */
+	strh	R3,	[R0, #0x08]	/* arm rhea control reg */
+	strh	R3,	[R1, #0x08]
+
+	/* enable IRQ and FIQ */
+
+	mrs	r4,	CPSR
+	bic	r4,	r4, #IRQ_MASK
+	bic	r4,	r4, #FIQ_MASK
+	msr	CPSR,	r4
+
+	/* set TAP CONF to TRI EMULATION */
+
+	ldr	r1,	[r0, #CONFIG_MODE2]
+	bic	r1,	r1, #0x18
+	orr	r1,	r1, #0x10
+	str	r1,	[r0, #CONFIG_MODE2]
+
+	/* set tdbgen to 1 */
+
+	ldr	r0,	PERSEUS2_CONFIG_BASE
+	ldr	r1,	[r0, #CONFIG_MODE1]
+	mov	r2,	#0x10000
+	orr	r1,	r1, r2
+	str	r1,	[r0, #CONFIG_MODE1]
+
+#ifdef CONFIG_P2_OMAP1610
+	/* inserting additional 2 clock cycle hold time for LAN */
+	ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
+	ldr	r1,     VAL_TC_EMIFS_CS1_ADVANCED
+	str     r1,     [r0]
+#endif
+	/* Start MPU Timer 1 */
+	ldr	r0,	REG_MPU_LOAD_TIMER
+	ldr	r1,	VAL_MPU_LOAD_TIMER
+	str	r1,	[r0]
+
+	ldr	r0,	REG_MPU_CNTL_TIMER
+	ldr	r1,	VAL_MPU_CNTL_TIMER
+	str	r1,	[r0]
+
+	/* back to arch calling code */
+	mov	pc,	r11
+
+	/* the literal pools origin */
+	.ltorg
+
+REG_TC_EMIFS_CONFIG:		/* 32 bits */
+	.word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
+	.word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
+	.word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
+	.word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
+	.word 0xfffecc1c
+
+#ifdef CONFIG_P2_OMAP730
+REG_TC_EMIFS_CS1_ADVANCED:	/* 32 bits */
+	.word 0xfffecc54
+#endif
+
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL:			/* 16 bits */
+	.word 0xfffece00
+
+REG_ARM_IDLECT3:		/* 16 bits */
+	.word 0xfffece24
+REG_ARM_IDLECT2:		/* 16 bits */
+	.word 0xfffece08
+REG_ARM_IDLECT1:		/* 16 bits */
+	.word 0xfffece04
+
+REG_ARM_RSTCT2:			/* 16 bits */
+	.word 0xfffece14
+REG_ARM_SYSST:			/* 16 bits */
+	.word 0xfffece18
+/* DPLL control registers */
+REG_DPLL1_CTL:			/* 16 bits */
+	.word 0xfffecf00
+
+/* Watch Dog register */
+/* secure watchdog stop */
+REG_WSPRDOG:
+	.word 0xfffeb048
+/* watchdog write pending */
+REG_WWPSDOG:
+	.word 0xfffeb034
+
+WSPRDOG_VAL1:
+	.word 0x0000aaaa
+WSPRDOG_VAL2:
+	.word 0x00005555
+
+/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
+ counter @8192 rows, 10 ns, 8 burst */
+REG_SDRAM_CONFIG:
+	.word 0xfffecc20
+
+REG_SDRAM_MRS_LEGACY:
+	.word 0xfffecc24
+
+REG_WATCHDOG:
+	.word 0xfffec808
+
+REG_MPU_LOAD_TIMER:
+	.word 0xfffec504
+REG_MPU_CNTL_TIMER:
+	.word 0xfffec500
+
+/* Public and private rhea bridge registers definition */
+
+REG_RHEA_PUB_CTL:
+	.word 0xFFFECA00
+
+REG_RHEA_PRIV_CTL:
+	.word 0xFFFED300
+
+/* EMIFF SDRAM Configuration register
+   - self refresh disable
+   - auto refresh enabled
+   - SDRAM type 64 Mb, 16 bits bus 4 banks
+   - power down enabled
+   - SDRAM clock disabled
+ */
+SDRAM_CONFIG_VAL:
+	.word 0x0C017DF4
+
+/* Burst full page length ; cas latency = 3 */
+SDRAM_MRS_VAL:
+	.word 0x00000037
+
+VAL_ARM_CKCTL:
+	.word 0x6505
+VAL_DPLL1_CTL:
+	.word 0x3412
+
+#ifdef CONFIG_P2_OMAP730
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x0000FFF3
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x00004278
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0x00004278
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x00004278
+VAL_TC_EMIFS_CS1_ADVANCED:
+	.word 0x00000022
+#endif
+
+VAL_ARM_IDLECT1:
+	.word 0x00000400
+VAL_ARM_IDLECT2:
+	.word 0x00000886
+VAL_ARM_IDLECT3:
+	.word 0x00000015
+
+WATCHDOG_VAL1:
+	.word 0x000000f5
+WATCHDOG_VAL2:
+	.word 0x000000a0
+
+VAL_MPU_LOAD_TIMER:
+	.word 0xffffffff
+VAL_MPU_CNTL_TIMER:
+	.word 0xffffffa1
+
+VAL_RHEA_CTL:
+	.word			0xFF22
+
+/* Config Register vals */
+PERSEUS2_CONFIG_BASE:
+	.word			0xFFFE1000
+
+.equ	CONFIG_PCC_CONF,	0xB4
+.equ	CONFIG_MODE1,		0x10
+.equ	CONFIG_MODE2,		0x14
+.equ	CONF_MOD_UART1_CLK_MODE_R,	0x0A
+
+/* misc values */
+.equ	IRQ_MASK,		0x80           /* IRQ mask value */
+.equ	FIQ_MASK,		0x40           /* FIQ mask value */
diff --git a/board/ti/omap730p2/omap730p2.c b/board/ti/omap730p2/omap730p2.c
new file mode 100644
index 0000000000..309d667585
--- /dev/null
+++ b/board/ti/omap730p2/omap730p2.c
@@ -0,0 +1,265 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_OMAP730)
+#include <./configs/omap730.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int test_boot_mode(void);
+void spin_up_leds(void);
+void flash__init (void);
+void ether__init (void);
+void set_muxconf_regs (void);
+void peripheral_power_enable (void);
+
+#define FLASH_ON_CS0	1
+#define FLASH_ON_CS3	0
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+			  "subs %0, %1, #1\n"
+			  "bne 1b":"=r" (loops):"0" (loops));
+}
+
+int test_boot_mode(void)
+{
+	/* Check for CS0 and CS3 address decode swapping */
+	if (*((volatile int *)EMIFS_CONFIG) & 0x00000002)
+		return(FLASH_ON_CS3);
+	else
+		return(FLASH_ON_CS0);
+}
+
+/* Toggle backup LED indication */
+void toggle_backup_led(void)
+{
+	static int  backupLEDState = 0;	 /* Init variable so that the LED will be ON the first time */
+	volatile unsigned int *IOConfReg;
+
+
+	IOConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT);
+
+	if (backupLEDState != 0) {
+		*IOConfReg &= (0xFFFFEFFF);
+		backupLEDState = 0;
+	} else {
+		*IOConfReg |= (0x00001000);
+		backupLEDState = 1;
+	}
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* arch number of OMAP 730 P2 Board - Same as the Innovator! */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP_PERSEUS2;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+	/* Configure MUX settings */
+	set_muxconf_regs ();
+
+	peripheral_power_enable ();
+
+	/* Backup LED indication via GPIO_140 -> Red led if MUX correctly setup */
+	toggle_backup_led();
+
+	/* Hold GSM in reset until needed */
+	*((volatile unsigned short *)M_CTL) &= ~1;
+
+	/*
+	 *  CSx timings, GPIO Mux ... setup
+	 */
+
+	/* Flash: CS0 timings setup */
+	*((volatile unsigned int *) FLASH_CFG_0) = 0x0000fff3;
+	*((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000088;
+
+	/* Ethernet support trough the debug board */
+	/* CS1 timings setup */
+	*((volatile unsigned int *) FLASH_CFG_1) = 0x0000fff3;
+	*((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000000;
+
+	/* this speeds up your boot a quite a bit.  However to make it
+	 *  work, you need make sure your kernel startup flush bug is fixed.
+	 *  ... rkw ...
+	 */
+	icache_enable ();
+
+	flash__init ();
+	ether__init ();
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	/* currently empty */
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+void flash__init (void)
+{
+	unsigned int regval;
+
+	regval = *((volatile unsigned int *) EMIFS_CONFIG);
+	/* Turn off write protection for flash devices. */
+	regval = regval | 0x0001;
+	*((volatile unsigned int *) EMIFS_CONFIG) = regval;
+}
+
+/*************************************************************
+ Routine:ether__init
+ Description: take the Ethernet controller out of reset and wait
+			   for the EEPROM load to complete.
+*************************************************************/
+void ether__init (void)
+{
+#define LAN_RESET_REGISTER 0x0400001c
+
+	*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
+	do {
+		*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001;
+		udelay (100);
+	} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001);
+
+	do {
+		*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
+		udelay (100);
+	} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000);
+
+#define ETH_CONTROL_REG 0x0400030b
+
+	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
+	udelay (100);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+/******************************************************
+ Routine: set_muxconf_regs
+ Description: Setting up the configuration Mux registers
+			  specific to the hardware
+*******************************************************/
+void set_muxconf_regs (void)
+{
+	volatile unsigned int *MuxConfReg;
+	/* set each registers to its reset value; */
+
+	/*
+	 *  Backup LED Indication
+	 */
+
+	/* Configure MUXed pin. Mode 6: GPIO_140 */
+	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF10);
+	*MuxConfReg &= (0xFFFFFF1F);	     /* Clear D_MPU_LPG1 */
+	*MuxConfReg |= 0x000000C0;	     /* Set D_MPU_LPG1 to 0x6 */
+
+	/* Configure GPIO_140 as output */
+	MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL);
+	*MuxConfReg &= (0xFFFFEFFF);	     /* Clear direction (output) for GPIO 140 */
+
+	/*
+	 * Configure GPIOs for battery charge & feedback
+	 */
+
+	/* Configure MUXed pin. Mode 6: GPIO_35 */
+	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3);
+	*MuxConfReg &= 0xFFFFFFF1;	     /* Clear M_CLK_OUT */
+	*MuxConfReg |= 0x0000000C;	     /* Set M_CLK_OUT = 0x6 (GPIOs) */
+
+	/* Configure MUXed pin. Mode 6: GPIO_72,73,74 */
+	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF5);
+	*MuxConfReg &= 0xFFFF1FFF;	     /* Clear D_DDR */
+	*MuxConfReg |= 0x0000C000;	     /* Set D_DDR = 0x6 (GPIOs) */
+
+	MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL);
+	*MuxConfReg |= 0x00000100;	     /* Configure GPIO_72 as input */
+	*MuxConfReg &= 0xFFFFFDFF;	     /* Configure GPIO_73 as output	*/
+
+	/*
+	 * Allow battery charge
+	 */
+
+	MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT);
+	*MuxConfReg &= (0xFFFFFDFF);	     /* Clear GPIO_73 pin */
+
+	/*
+	 * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
+	 * It is used as the Ethernet controller interrupt
+	 */
+	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF9);
+	*MuxConfReg &= 0x1FFFFFFF;
+}
+
+/******************************************************
+ Routine: peripheral_power_enable
+ Description: Enable the power for UART1
+*******************************************************/
+void peripheral_power_enable (void)
+{
+	volatile unsigned int *MuxConfReg;
+
+
+	/* Set up pins used by UART */
+
+	/* Start UART clock (48MHz) */
+	MuxConfReg = (volatile unsigned int *) (PERSEUS_PCC_CONF_REG);
+	*MuxConfReg &= (0xFFFFFFF7);
+	*MuxConfReg |= (0x00000008);
+
+	/* Get the UART pin in mode0  */
+	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3);
+	*MuxConfReg &= (0xFF1FFFFF);
+	*MuxConfReg &= (0xF1FFFFFF);
+}
author	Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>	2009-08-23 16:32:38 +0200
committer	Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>	2009-09-05 01:33:09 +0200
commit	0a0e4bad9693ef1d2ca8c33ba551d395a4e3d641 (patch)
tree	77fe8fd938e959924120b59932cd24c3fecd78cf /board/ti
parent	2dc851e3b0f07a56f83060f13882ff4b62cf5112 (diff)