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authorLokesh Vutla <lokeshvutla@ti.com>2016-04-13 09:50:59 +0530
committerTom Rini <trini@konsulko.com>2016-04-18 17:11:43 -0400
commit8f69523213a2929fda1fb62fe018684444586c1b (patch)
treed5e69ab1ccec48b7efc5e93362a49e03eae7f886 /board/ti
parent3bfc8152b2c09d81fb00f4d3990e5dfd59682b96 (diff)
memory: Move TI_AEMIF config to KCONFIG
Not all Keystone2 devices has AEMIF NAND controller. So adding Kconfig entry for CONFIG_TI_AEMIF and enabling it in respective defconfigs on platforms with AEMIF controller. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'board/ti')
-rw-r--r--board/ti/ks2_evm/board.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index e16669da08..9e8ad932d4 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -20,6 +20,7 @@
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_TI_AEMIF)
static struct aemif_config aemif_configs[] = {
{ /* CS0 */
.mode = AEMIF_MODE_NAND,
@@ -33,6 +34,7 @@ static struct aemif_config aemif_configs[] = {
.width = AEMIF_WIDTH_8,
},
};
+#endif
int dram_init(void)
{
@@ -42,7 +44,10 @@ int dram_init(void)
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
+#if defined(CONFIG_TI_AEMIF)
aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
+#endif
+
if (ddr3_size)
ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
return 0;