Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

16 files changed, 589 insertions, 420 deletions

diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index da780edb89..d81eec90b4 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -84,41 +84,17 @@ static int read_eeprom(struct am335x_baseboard_id *header)
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 static const struct ddr_data ddr2_data = {
-	.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
-			  (MT47H128M16RT25E_RD_DQS<<20) |
-			  (MT47H128M16RT25E_RD_DQS<<10) |
-			  (MT47H128M16RT25E_RD_DQS<<0)),
-	.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
-			  (MT47H128M16RT25E_WR_DQS<<20) |
-			  (MT47H128M16RT25E_WR_DQS<<10) |
-			  (MT47H128M16RT25E_WR_DQS<<0)),
-	.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
-			 (MT47H128M16RT25E_PHY_WRLVL<<20) |
-			 (MT47H128M16RT25E_PHY_WRLVL<<10) |
-			 (MT47H128M16RT25E_PHY_WRLVL<<0)),
-	.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
-			 (MT47H128M16RT25E_PHY_GATELVL<<20) |
-			 (MT47H128M16RT25E_PHY_GATELVL<<10) |
-			 (MT47H128M16RT25E_PHY_GATELVL<<0)),
-	.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
-			  (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
-			  (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
-			  (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
-	.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
-			  (MT47H128M16RT25E_PHY_WR_DATA<<20) |
-			  (MT47H128M16RT25E_PHY_WR_DATA<<10) |
-			  (MT47H128M16RT25E_PHY_WR_DATA<<0)),
+	.datardsratio0 = MT47H128M16RT25E_RD_DQS,
+	.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
+	.datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
 };
 
 static const struct cmd_control ddr2_cmd_ctrl_data = {
 	.cmd0csratio = MT47H128M16RT25E_RATIO,
-	.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 
 	.cmd1csratio = MT47H128M16RT25E_RATIO,
-	.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 
 	.cmd2csratio = MT47H128M16RT25E_RATIO,
-	.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 };
 
 static const struct emif_regs ddr2_emif_reg_data = {
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 7e239f1c88..51fa9e04a3 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -19,6 +19,7 @@
 #include <asm/arch/gpio.h>
 #include <asm/emif.h>
 #include "board.h"
+#include <power/pmic.h>
 #include <power/tps65218.h>
 #include <miiphy.h>
 #include <cpsw.h>
@@ -605,6 +606,19 @@ void sdram_init(void)
 }
 #endif
 
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+	struct pmic *p;
+
+	power_tps65218_init(I2C_PMIC);
+	p = pmic_get("TPS65218_PMIC");
+	if (p && !pmic_probe(p))
+		puts("PMIC:  TPS65218\n");
+
+	return 0;
+}
+
 int board_init(void)
 {
 	struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 7f19655cfe..ae50d88c57 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -163,6 +163,8 @@ int spl_start_uboot(void)
 #define VIN2A_D15_DLY_VAL		((0x4 << 5) + 0x0)
 #define VIN2A_D14_DLY_VAL		((0x4 << 5) + 0x0)
 
+extern u32 *const omap_si_rev;
+
 static void cpsw_control(int enabled)
 {
 	/* VTP can be added here */
@@ -189,7 +191,7 @@ static struct cpsw_platform_data cpsw_data = {
 	.mdio_div		= 0xff,
 	.channels		= 8,
 	.cpdma_reg_ofs		= 0x800,
-	.slaves			= 1,
+	.slaves			= 2,
 	.slave_data		= cpsw_slaves,
 	.ale_reg_ofs		= 0xd00,
 	.ale_entries		= 1024,
@@ -260,6 +262,9 @@ int board_eth_init(bd_t *bis)
 	ctrl_val |= 0x22;
 	writel(ctrl_val, (*ctrl)->control_core_control_io1);
 
+	if (*omap_si_rev == DRA722_ES1_0)
+		cpsw_data.active_slave = 1;
+
 	ret = cpsw_register(&cpsw_data);
 	if (ret < 0)
 		printf("Error %d registering CPSW switch\n", ret);
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index c9e202af68..7db70324e9 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -56,6 +56,18 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
 	{RGMII0_RXD2, (IEN | M0) },
 	{RGMII0_RXD1, (IEN | M0) },
 	{RGMII0_RXD0, (IEN | M0) },
+	{VIN2A_D12, (M3) },
+	{VIN2A_D13, (M3) },
+	{VIN2A_D14, (M3) },
+	{VIN2A_D15, (M3) },
+	{VIN2A_D16, (M3) },
+	{VIN2A_D17, (M3) },
+	{VIN2A_D18, (IEN | M3)},
+	{VIN2A_D19, (IEN | M3)},
+	{VIN2A_D20, (IEN | M3)},
+	{VIN2A_D21, (IEN | M3)},
+	{VIN2A_D22, (IEN | M3)},
+	{VIN2A_D23, (IEN | M3)},
 	{GPMC_A13, (IEN | PDIS | M1)},  /* QSPI1_RTCLK */
 	{GPMC_A14, (IEN | PDIS | M1)},  /* QSPI1_D[3] */
 	{GPMC_A15, (IEN | PDIS | M1)},  /* QSPI1_D[2] */
diff --git a/board/ti/k2hk_evm/Makefile b/board/ti/k2hk_evm/Makefile
deleted file mode 100644
index 3645f2feb0..0000000000
--- a/board/ti/k2hk_evm/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# K2HK-EVM: board Makefile
-# (C) Copyright 2012-2014
-#     Texas Instruments Incorporated, <www.ti.com>
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y	+= board.o
-obj-y	+= ddr3.o
diff --git a/board/ti/k2hk_evm/ddr3.c b/board/ti/k2hk_evm/ddr3.c
deleted file mode 100644
index 6092eb8fe3..0000000000
--- a/board/ti/k2hk_evm/ddr3.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * Keystone2: DDR3 initialization
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <i2c.h>
-
-/************************* *****************************/
-static struct ddr3_phy_config ddr3phy_1600_64A = {
-	.pllcr		= 0x0001C000ul,
-	.pgcr1_mask	= (IODDRM_MASK | ZCKSEL_MASK),
-	.pgcr1_val	= ((1 << 2) | (1 << 7) | (1 << 23)),
-	.ptr0		= 0x42C21590ul,
-	.ptr1		= 0xD05612C0ul,
-	.ptr2		= 0, /* not set in gel */
-	.ptr3		= 0x0D861A80ul,
-	.ptr4		= 0x0C827100ul,
-	.dcr_mask	= (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
-	.dcr_val	= ((1 << 10) | (1 << 27)),
-	.dtpr0		= 0xA19DBB66ul,
-	.dtpr1		= 0x12868300ul,
-	.dtpr2		= 0x50035200ul,
-	.mr0		= 0x00001C70ul,
-	.mr1		= 0x00000006ul,
-	.mr2		= 0x00000018ul,
-	.dtcr		= 0x730035C7ul,
-	.pgcr2		= 0x00F07A12ul,
-	.zq0cr1		= 0x0000005Dul,
-	.zq1cr1		= 0x0000005Bul,
-	.zq2cr1		= 0x0000005Bul,
-	.pir_v1		= 0x00000033ul,
-	.pir_v2		= 0x0000FF81ul,
-};
-
-static struct ddr3_emif_config ddr3_1600_64 = {
-	.sdcfg		= 0x6200CE6aul,
-	.sdtim1		= 0x16709C55ul,
-	.sdtim2		= 0x00001D4Aul,
-	.sdtim3		= 0x435DFF54ul,
-	.sdtim4		= 0x553F0CFFul,
-	.zqcfg		= 0xF0073200ul,
-	.sdrfc		= 0x00001869ul,
-};
-
-static struct ddr3_phy_config ddr3phy_1600_32 = {
-	.pllcr		= 0x0001C000ul,
-	.pgcr1_mask	= (IODDRM_MASK | ZCKSEL_MASK),
-	.pgcr1_val	= ((1 << 2) | (1 << 7) | (1 << 23)),
-	.ptr0		= 0x42C21590ul,
-	.ptr1		= 0xD05612C0ul,
-	.ptr2		= 0, /* not set in gel */
-	.ptr3		= 0x0D861A80ul,
-	.ptr4		= 0x0C827100ul,
-	.dcr_mask	= (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
-	.dcr_val	= ((1 << 10) | (1 << 27)),
-	.dtpr0		= 0xA19DBB66ul,
-	.dtpr1		= 0x12868300ul,
-	.dtpr2		= 0x50035200ul,
-	.mr0		= 0x00001C70ul,
-	.mr1		= 0x00000006ul,
-	.mr2		= 0x00000018ul,
-	.dtcr		= 0x730035C7ul,
-	.pgcr2		= 0x00F07A12ul,
-	.zq0cr1		= 0x0000005Dul,
-	.zq1cr1		= 0x0000005Bul,
-	.zq2cr1		= 0x0000005Bul,
-	.pir_v1		= 0x00000033ul,
-	.pir_v2		= 0x0000FF81ul,
-};
-
-static struct ddr3_emif_config ddr3_1600_32 = {
-	.sdcfg		= 0x6200DE6aul,
-	.sdtim1		= 0x16709C55ul,
-	.sdtim2		= 0x00001D4Aul,
-	.sdtim3		= 0x435DFF54ul,
-	.sdtim4		= 0x553F0CFFul,
-	.zqcfg		= 0x70073200ul,
-	.sdrfc		= 0x00001869ul,
-};
-
-/************************* *****************************/
-static struct ddr3_phy_config ddr3phy_1333_64A = {
-	.pllcr		= 0x0005C000ul,
-	.pgcr1_mask	= (IODDRM_MASK | ZCKSEL_MASK),
-	.pgcr1_val	= ((1 << 2) | (1 << 7) | (1 << 23)),
-	.ptr0		= 0x42C21590ul,
-	.ptr1		= 0xD05612C0ul,
-	.ptr2		= 0, /* not set in gel */
-	.ptr3		= 0x0B4515C2ul,
-	.ptr4		= 0x0A6E08B4ul,
-	.dcr_mask	= (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
-			   NOSRA_MASK | UDIMM_MASK),
-	.dcr_val	= ((1 << 10) | (1 << 27) | (1 << 29)),
-	.dtpr0		= 0x8558AA55ul,
-	.dtpr1		= 0x12857280ul,
-	.dtpr2		= 0x5002C200ul,
-	.mr0		= 0x00001A60ul,
-	.mr1		= 0x00000006ul,
-	.mr2		= 0x00000010ul,
-	.dtcr		= 0x710035C7ul,
-	.pgcr2		= 0x00F065B8ul,
-	.zq0cr1		= 0x0000005Dul,
-	.zq1cr1		= 0x0000005Bul,
-	.zq2cr1		= 0x0000005Bul,
-	.pir_v1		= 0x00000033ul,
-	.pir_v2		= 0x0000FF81ul,
-};
-
-static struct ddr3_emif_config ddr3_1333_64 = {
-	.sdcfg		= 0x62008C62ul,
-	.sdtim1		= 0x125C8044ul,
-	.sdtim2		= 0x00001D29ul,
-	.sdtim3		= 0x32CDFF43ul,
-	.sdtim4		= 0x543F0ADFul,
-	.zqcfg		= 0xF0073200ul,
-	.sdrfc		= 0x00001457ul,
-};
-
-static struct ddr3_phy_config ddr3phy_1333_32 = {
-	.pllcr		= 0x0005C000ul,
-	.pgcr1_mask	= (IODDRM_MASK | ZCKSEL_MASK),
-	.pgcr1_val	= ((1 << 2) | (1 << 7) | (1 << 23)),
-	.ptr0		= 0x42C21590ul,
-	.ptr1		= 0xD05612C0ul,
-	.ptr2		= 0, /* not set in gel */
-	.ptr3		= 0x0B4515C2ul,
-	.ptr4		= 0x0A6E08B4ul,
-	.dcr_mask	= (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
-			   NOSRA_MASK | UDIMM_MASK),
-	.dcr_val	= ((1 << 10) | (1 << 27) | (1 << 29)),
-	.dtpr0		= 0x8558AA55ul,
-	.dtpr1		= 0x12857280ul,
-	.dtpr2		= 0x5002C200ul,
-	.mr0		= 0x00001A60ul,
-	.mr1		= 0x00000006ul,
-	.mr2		= 0x00000010ul,
-	.dtcr		= 0x710035C7ul,
-	.pgcr2		= 0x00F065B8ul,
-	.zq0cr1		= 0x0000005Dul,
-	.zq1cr1		= 0x0000005Bul,
-	.zq2cr1		= 0x0000005Bul,
-	.pir_v1		= 0x00000033ul,
-	.pir_v2		= 0x0000FF81ul,
-};
-
-static struct ddr3_emif_config ddr3_1333_32 = {
-	.sdcfg		= 0x62009C62ul,
-	.sdtim1		= 0x125C8044ul,
-	.sdtim2		= 0x00001D29ul,
-	.sdtim3		= 0x32CDFF43ul,
-	.sdtim4		= 0x543F0ADFul,
-	.zqcfg		= 0xf0073200ul,
-	.sdrfc		= 0x00001457ul,
-};
-
-/************************* *****************************/
-static struct ddr3_phy_config ddr3phy_1333_64 = {
-	.pllcr		= 0x0005C000ul,
-	.pgcr1_mask	= (IODDRM_MASK | ZCKSEL_MASK),
-	.pgcr1_val	= ((1 << 2) | (1 << 7) | (1 << 23)),
-	.ptr0		= 0x42C21590ul,
-	.ptr1		= 0xD05612C0ul,
-	.ptr2		= 0, /* not set in gel */
-	.ptr3		= 0x0B4515C2ul,
-	.ptr4		= 0x0A6E08B4ul,
-	.dcr_mask	= (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
-	.dcr_val	= ((1 << 10) | (1 << 27)),
-	.dtpr0		= 0x8558AA55ul,
-	.dtpr1		= 0x12857280ul,
-	.dtpr2		= 0x5002C200ul,
-	.mr0		= 0x00001A60ul,
-	.mr1		= 0x00000006ul,
-	.mr2		= 0x00000010ul,
-	.dtcr		= 0x710035C7ul,
-	.pgcr2		= 0x00F065B8ul,
-	.zq0cr1		= 0x0000005Dul,
-	.zq1cr1		= 0x0000005Bul,
-	.zq2cr1		= 0x0000005Bul,
-	.pir_v1		= 0x00000033ul,
-	.pir_v2		= 0x0000FF81ul,
-};
-/******************************************************/
-int get_dimm_params(char *dimm_name)
-{
-	u8 spd_params[256];
-	int ret;
-	int old_bus;
-
-	i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
-
-	old_bus = i2c_get_bus_num();
-	i2c_set_bus_num(1);
-
-	ret = i2c_read(0x53, 0, 1, spd_params, 256);
-
-	i2c_set_bus_num(old_bus);
-
-	dimm_name[0] = '\0';
-
-	if (ret) {
-		puts("Cannot read DIMM params\n");
-		return 1;
-	}
-
-	/*
-	 * We need to convert spd data to dimm parameters
-	 * and to DDR3 EMIF and PHY regirsters values.
-	 * For now we just return DIMM type string value.
-	 * Caller may use this value to choose appropriate
-	 * a pre-set DDR3 configuration
-	 */
-
-	strncpy(dimm_name, (char *)&spd_params[0x80], 18);
-	dimm_name[18] = '\0';
-
-	return 0;
-}
-
-struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
-struct pll_init_data ddr3b_333 = DDR3_PLL_333(B);
-struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
-struct pll_init_data ddr3b_400 = DDR3_PLL_400(B);
-
-void init_ddr3(void)
-{
-	char dimm_name[32];
-
-	get_dimm_params(dimm_name);
-
-	printf("Detected SO-DIMM [%s]\n", dimm_name);
-
-	if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
-		init_pll(&ddr3a_400);
-		if (cpu_revision() > 0) {
-			init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_64A);
-			init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_64);
-			printf("DRAM:  Capacity 8 GiB (includes reported below)\n");
-		} else {
-			init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_32);
-			init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_32);
-			printf("DRAM:  Capacity 4 GiB (includes reported below)\n");
-		}
-	} else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
-		init_pll(&ddr3a_333);
-		if (cpu_revision() > 0) {
-			init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_64A);
-			init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_64);
-		} else {
-			init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_32);
-			init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_32);
-		}
-	} else {
-		printf("Unknown SO-DIMM. Cannot configure DDR3\n");
-		while (1)
-			;
-	}
-
-	init_pll(&ddr3b_333);
-	init_ddrphy(K2HK_DDR3B_DDRPHYC, &ddr3phy_1333_64);
-	init_ddremif(K2HK_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64);
-}
diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile
new file mode 100644
index 0000000000..00f1164833
--- /dev/null
+++ b/board/ti/ks2_evm/Makefile
@@ -0,0 +1,13 @@
+#
+# KS2-EVM: board Makefile
+# (C) Copyright 2012-2014
+#     Texas Instruments Incorporated, <www.ti.com>
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y += board.o
+obj-y += ddr3_cfg.o
+obj-$(CONFIG_K2HK_EVM) += board_k2hk.o
+obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
+obj-$(CONFIG_K2E_EVM) += board_k2e.o
+obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o
diff --git a/board/ti/k2hk_evm/README b/board/ti/ks2_evm/README_K2HK
index bfeb05b4a4..7426b8dc97 100644
--- a/board/ti/k2hk_evm/README
+++ b/board/ti/ks2_evm/README_K2HK
@@ -38,11 +38,13 @@ board configuration file: include/configs/k2hk_evm.h
 
 Supported boot modes:
  - SPI NOR boot
+ - AEMIF NAND boot
 
 Supported image formats:-
  - u-boot.bin: for loading and running u-boot.bin through Texas instruments
                code composure studio (CCS)
  - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot
+ - u-boot-nand.gph: gpimage for programming AEMIF NAND flash for NAND boot
 
 Build instructions:
 ===================
@@ -55,6 +57,10 @@ To build u-boot-spi.gph
   >make k2hk_evm_config
   >make u-boot-spi.gph
 
+To build u-boot-nand.gph
+  >make k2hk_evm_config
+  >make u-boot-nand.gph
+
 Load and Run U-Boot on K2HK EVM using CCS
 =========================================
 
@@ -115,8 +121,28 @@ instructions:-
 5. At the U-Boot console type following to setup u-boot environment variables.
    setenv addr_uboot 0x87000000
    setenv filesize <size in hex of u-boot-spi.gph rounded to hex 0x10000>
-   run burn_uboot
+   run burn_uboot_spi
    Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
    to "SPI Little Endian Boot mode" as per instruction at
    http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup.
 6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash.
+
+AEMIF NAND Flash programming instructions
+======================================
+U-Boot image can be flashed to first 1024KB of the NAND flash using following
+instructions:-
+
+1. Start CCS and run U-boot as described above.
+2. Suspend Target. Select Run -> Suspend from top level menu
+   CortexA15_1 (Free Running)"
+3. Load u-boot-nand.gph binary from build folder on to DDR address 0x87000000
+   through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM
+   using CCS", but using address 0x87000000.
+4. Free Run the target as desribed earlier (step 4) to get u-boot prompt
+5. At the U-Boot console type following to setup u-boot environment variables.
+   setenv filesize <size in hex of u-boot-nand.gph rounded to hex 0x10000>
+   run burn_uboot_nand
+   Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
+   to "ARM NAND Boot mode" as per instruction at
+   http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup.
+6. Power ON the EVM. The EVM now boots with u-boot image on the NAND flash.
diff --git a/board/ti/k2hk_evm/board.c b/board/ti/ks2_evm/board.c
index ef90f9d821..dfe7be60e7 100644
--- a/board/ti/k2hk_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -1,45 +1,22 @@
 /*
- * K2HK EVM : Board initialization
+ * Keystone : Board initialization
  *
- * (C) Copyright 2012-2014
+ * (C) Copyright 2014
  *     Texas Instruments Incorporated, <www.ti.com>
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
 
+#include "board.h"
 #include <common.h>
 #include <exports.h>
 #include <fdt_support.h>
-#include <libfdt.h>
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/clock.h>
-#include <asm/io.h>
-#include <asm/mach-types.h>
+#include <asm/arch/ddr3.h>
 #include <asm/arch/emac_defs.h>
-#include <asm/arch/psc_defs.h>
 #include <asm/ti-common/ti-aemif.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-u32 device_big_endian;
-
-unsigned int external_clk[ext_clk_count] = {
-	[sys_clk]	=	122880000,
-	[alt_core_clk]	=	125000000,
-	[pa_clk]	=	122880000,
-	[tetris_clk]	=	125000000,
-	[ddr3a_clk]	=	100000000,
-	[ddr3b_clk]	=	100000000,
-	[mcm_clk]	=	312500000,
-	[pcie_clk]	=	100000000,
-	[sgmii_srio_clk] =	156250000,
-	[xgmii_clk]	=	156250000,
-	[usb_clk]	=	100000000,
-	[rp1_clk]	=	123456789    /* TODO: cannot find
-						what is that */
-};
-
 static struct aemif_config aemif_configs[] = {
 	{			/* CS0 */
 		.mode		= AEMIF_MODE_NAND,
@@ -52,18 +29,11 @@ static struct aemif_config aemif_configs[] = {
 		.turn_around	= 3,
 		.width		= AEMIF_WIDTH_8,
 	},
-
-};
-
-static struct pll_init_data pll_config[] = {
-	CORE_PLL_1228,
-	PASS_PLL_983,
-	TETRIS_PLL_1200,
 };
 
 int dram_init(void)
 {
-	init_ddr3();
+	ddr3_init();
 
 	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 				    CONFIG_MAX_RAM_BANK_SIZE);
@@ -71,42 +41,18 @@ int dram_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
-struct eth_priv_t eth_priv_cfg[] = {
-	{
-		.int_name	= "K2HK_EMAC",
-		.rx_flow	= 22,
-		.phy_addr	= 0,
-		.slave_port	= 1,
-		.sgmii_link_type = SGMII_LINK_MAC_PHY,
-	},
-	{
-		.int_name	= "K2HK_EMAC1",
-		.rx_flow	= 23,
-		.phy_addr	= 1,
-		.slave_port	= 2,
-		.sgmii_link_type = SGMII_LINK_MAC_PHY,
-	},
-	{
-		.int_name	= "K2HK_EMAC2",
-		.rx_flow	= 24,
-		.phy_addr	= 2,
-		.slave_port	= 3,
-		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
-	},
-	{
-		.int_name	= "K2HK_EMAC3",
-		.rx_flow	= 25,
-		.phy_addr	= 3,
-		.slave_port	= 4,
-		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
-	},
-};
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CONFIG_LINUX_BOOT_PARAM_ADDR;
+
+	return 0;
+}
 
+#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
 int get_eth_env_param(char *env_name)
 {
 	char *env;
-	int  res = -1;
+	int res = -1;
 
 	env = getenv(env_name);
 	if (env)
@@ -117,12 +63,14 @@ int get_eth_env_param(char *env_name)
 
 int board_eth_init(bd_t *bis)
 {
-	int	j;
-	int	res;
-	char	link_type_name[32];
+	int j;
+	int res;
+	int port_num;
+	char link_type_name[32];
 
-	for (j = 0; j < (sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t));
-	     j++) {
+	port_num = get_num_eth_ports();
+
+	for (j = 0; j < port_num; j++) {
 		sprintf(link_type_name, "sgmii%d_link_type", j);
 		res = get_eth_env_param(link_type_name);
 		if (res >= 0)
@@ -135,46 +83,24 @@ int board_eth_init(bd_t *bis)
 }
 #endif
 
-/* Byte swap the 32-bit data if the device is BE */
-int cpu_to_bus(u32 *ptr, u32 length)
-{
-	u32 i;
-
-	if (device_big_endian)
-		for (i = 0; i < length; i++, ptr++)
-			*ptr = __swab32(*ptr);
-
-	return 0;
-}
-
-#if defined(CONFIG_BOARD_EARLY_INIT_F)
-int board_early_init_f(void)
-{
-	init_plls(ARRAY_SIZE(pll_config), pll_config);
-	return 0;
-}
-#endif
-
-int board_init(void)
-{
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-	return 0;
-}
-
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-#define K2_DDR3_START_ADDR 0x80000000
 void ft_board_setup(void *blob, bd_t *bd)
 {
-	u64 start[2];
+	int lpae;
+	char *env;
+	char *endp;
+	int nbanks;
 	u64 size[2];
-	char name[32], *env, *endp;
-	int lpae, nodeoffset;
+	u64 start[2];
+	char name[32];
+	int nodeoffset;
 	u32 ddr3a_size;
-	int nbanks;
+	int unitrd_fixup = 0;
 
 	env = getenv("mem_lpae");
 	lpae = env && simple_strtol(env, NULL, 0);
+	env = getenv("uinitrd_fixup");
+	unitrd_fixup = env && simple_strtol(env, NULL, 0);
 
 	ddr3a_size = 0;
 	if (lpae) {
@@ -191,7 +117,7 @@ void ft_board_setup(void *blob, bd_t *bd)
 
 	/* adjust memory start address for LPAE */
 	if (lpae) {
-		start[0] -= K2_DDR3_START_ADDR;
+		start[0] -= CONFIG_SYS_SDRAM_BASE;
 		start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
 	}
 
@@ -217,10 +143,11 @@ void ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_memory_banks(blob, start, size, nbanks);
 
 	/* Fix up the initrd */
-	if (lpae) {
-		u64 initrd_start, initrd_end;
-		u32 *prop1, *prop2;
+	if (lpae && unitrd_fixup) {
 		int err;
+		u32 *prop1, *prop2;
+		u64 initrd_start, initrd_end;
+
 		nodeoffset = fdt_path_offset(blob, "/chosen");
 		if (nodeoffset >= 0) {
 			prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
@@ -229,11 +156,11 @@ void ft_board_setup(void *blob, bd_t *bd)
 					    "linux,initrd-end", NULL);
 			if (prop1 && prop2) {
 				initrd_start = __be32_to_cpu(*prop1);
-				initrd_start -= K2_DDR3_START_ADDR;
+				initrd_start -= CONFIG_SYS_SDRAM_BASE;
 				initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
 				initrd_start = __cpu_to_be64(initrd_start);
 				initrd_end = __be32_to_cpu(*prop2);
-				initrd_end -= K2_DDR3_START_ADDR;
+				initrd_end -= CONFIG_SYS_SDRAM_BASE;
 				initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
 				initrd_end = __cpu_to_be64(initrd_end);
 
@@ -267,9 +194,10 @@ void ft_board_setup(void *blob, bd_t *bd)
 
 void ft_board_setup_ex(void *blob, bd_t *bd)
 {
-	int	lpae;
-	char	*env;
-	u64	*reserve_start, size;
+	int lpae;
+	u64 size;
+	char *env;
+	u64 *reserve_start;
 
 	env = getenv("mem_lpae");
 	lpae = env && simple_strtol(env, NULL, 0);
@@ -286,7 +214,7 @@ void ft_board_setup_ex(void *blob, bd_t *bd)
 			*reserve_start = __cpu_to_be64(*reserve_start);
 			size = __cpu_to_be64(*(reserve_start + 1));
 			if (size) {
-				*reserve_start -= K2_DDR3_START_ADDR;
+				*reserve_start -= CONFIG_SYS_SDRAM_BASE;
 				*reserve_start +=
 					CONFIG_SYS_LPAE_SDRAM_BASE;
 				*reserve_start =
diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h
new file mode 100644
index 0000000000..d91ef73612
--- /dev/null
+++ b/board/ti/ks2_evm/board.h
@@ -0,0 +1,19 @@
+/*
+ * K2HK EVM : Board common header
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _KS2_BOARD
+#define _KS2_BOARD
+
+#include <asm/arch/emac_defs.h>
+
+extern struct eth_priv_t eth_priv_cfg[];
+
+int get_num_eth_ports(void);
+
+#endif
diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
new file mode 100644
index 0000000000..d2499b7244
--- /dev/null
+++ b/board/ti/ks2_evm/board_k2e.c
@@ -0,0 +1,39 @@
+/*
+ * K2E EVM : Board initialization
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int external_clk[ext_clk_count] = {
+	[sys_clk]	= 100000000,
+	[alt_core_clk]	= 100000000,
+	[pa_clk]	= 100000000,
+	[ddr3_clk]	= 100000000,
+	[mcm_clk]	= 312500000,
+	[pcie_clk]	= 100000000,
+	[sgmii_clk]	= 156250000,
+	[xgmii_clk]	= 156250000,
+	[usb_clk]	= 100000000,
+};
+
+static struct pll_init_data pll_config[] = {
+	CORE_PLL_1200,
+	PASS_PLL_1000,
+};
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+	init_plls(ARRAY_SIZE(pll_config), pll_config);
+	return 0;
+}
+#endif
diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c
new file mode 100644
index 0000000000..a369d6bd63
--- /dev/null
+++ b/board/ti/ks2_evm/board_k2hk.c
@@ -0,0 +1,81 @@
+/*
+ * K2HK EVM : Board initialization
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emac_defs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int external_clk[ext_clk_count] = {
+	[sys_clk]	=	122880000,
+	[alt_core_clk]	=	125000000,
+	[pa_clk]	=	122880000,
+	[tetris_clk]	=	125000000,
+	[ddr3a_clk]	=	100000000,
+	[ddr3b_clk]	=	100000000,
+	[mcm_clk]	=	312500000,
+	[pcie_clk]	=	100000000,
+	[sgmii_srio_clk] =	156250000,
+	[xgmii_clk]	=	156250000,
+	[usb_clk]	=	100000000,
+	[rp1_clk]	=	123456789
+};
+
+static struct pll_init_data pll_config[] = {
+	CORE_PLL_1228,
+	PASS_PLL_983,
+	TETRIS_PLL_1200,
+};
+
+#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
+struct eth_priv_t eth_priv_cfg[] = {
+	{
+		.int_name	= "K2HK_EMAC",
+		.rx_flow	= 22,
+		.phy_addr	= 0,
+		.slave_port	= 1,
+		.sgmii_link_type = SGMII_LINK_MAC_PHY,
+	},
+	{
+		.int_name	= "K2HK_EMAC1",
+		.rx_flow	= 23,
+		.phy_addr	= 1,
+		.slave_port	= 2,
+		.sgmii_link_type = SGMII_LINK_MAC_PHY,
+	},
+	{
+		.int_name	= "K2HK_EMAC2",
+		.rx_flow	= 24,
+		.phy_addr	= 2,
+		.slave_port	= 3,
+		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+	},
+	{
+		.int_name	= "K2HK_EMAC3",
+		.rx_flow	= 25,
+		.phy_addr	= 3,
+		.slave_port	= 4,
+		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+	},
+};
+
+int get_num_eth_ports(void)
+{
+	return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	init_plls(ARRAY_SIZE(pll_config), pll_config);
+	return 0;
+}
+#endif
diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c
new file mode 100644
index 0000000000..f7da9f2bcb
--- /dev/null
+++ b/board/ti/ks2_evm/ddr3_cfg.c
@@ -0,0 +1,170 @@
+/*
+ * Keystone2: DDR3 configuration
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <i2c.h>
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* DDR3 PHY configuration data with 1600M rate, 8GB size */
+struct ddr3_phy_config ddr3phy_1600_8g = {
+	.pllcr          = 0x0001C000ul,
+	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
+	.pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
+	.ptr0           = 0x42C21590ul,
+	.ptr1           = 0xD05612C0ul,
+	.ptr2           = 0, /* not set in gel */
+	.ptr3           = 0x0D861A80ul,
+	.ptr4           = 0x0C827100ul,
+	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+	.dcr_val        = ((1 << 10)),
+	.dtpr0          = 0xA19DBB66ul,
+	.dtpr1          = 0x32868300ul,
+	.dtpr2          = 0x50035200ul,
+	.mr0            = 0x00001C70ul,
+	.mr1            = 0x00000006ul,
+	.mr2            = 0x00000018ul,
+	.dtcr           = 0x730035C7ul,
+	.pgcr2          = 0x00F07A12ul,
+	.zq0cr1         = 0x0000005Dul,
+	.zq1cr1         = 0x0000005Bul,
+	.zq2cr1         = 0x0000005Bul,
+	.pir_v1         = 0x00000033ul,
+	.pir_v2         = 0x0000FF81ul,
+};
+
+/* DDR3 EMIF configuration data with 1600M rate, 8GB size */
+struct ddr3_emif_config ddr3_1600_8g = {
+	.sdcfg          = 0x6200CE6Aul,
+	.sdtim1         = 0x16709C55ul,
+	.sdtim2         = 0x00001D4Aul,
+	.sdtim3         = 0x435DFF54ul,
+	.sdtim4         = 0x553F0CFFul,
+	.zqcfg          = 0xF0073200ul,
+	.sdrfc          = 0x00001869ul,
+};
+
+#ifdef CONFIG_K2HK_EVM
+/* DDR3 PHY configuration data with 1333M rate, and 2GB size */
+struct ddr3_phy_config ddr3phy_1333_2g = {
+	.pllcr          = 0x0005C000ul,
+	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
+	.pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
+	.ptr0           = 0x42C21590ul,
+	.ptr1           = 0xD05612C0ul,
+	.ptr2           = 0, /* not set in gel */
+	.ptr3           = 0x0B4515C2ul,
+	.ptr4           = 0x0A6E08B4ul,
+	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+	.dcr_val        = ((1 << 10)),
+	.dtpr0          = 0x8558AA55ul,
+	.dtpr1          = 0x32857280ul,
+	.dtpr2          = 0x5002C200ul,
+	.mr0            = 0x00001A60ul,
+	.mr1            = 0x00000006ul,
+	.mr2            = 0x00000010ul,
+	.dtcr           = 0x710035C7ul,
+	.pgcr2          = 0x00F065B8ul,
+	.zq0cr1         = 0x0000005Dul,
+	.zq1cr1         = 0x0000005Bul,
+	.zq2cr1         = 0x0000005Bul,
+	.pir_v1         = 0x00000033ul,
+	.pir_v2         = 0x0000FF81ul,
+};
+
+/* DDR3 EMIF configuration data with 1333M rate, and 2GB size */
+struct ddr3_emif_config ddr3_1333_2g = {
+	.sdcfg          = 0x62008C62ul,
+	.sdtim1         = 0x125C8044ul,
+	.sdtim2         = 0x00001D29ul,
+	.sdtim3         = 0x32CDFF43ul,
+	.sdtim4         = 0x543F0ADFul,
+	.zqcfg          = 0x70073200ul,
+	.sdrfc          = 0x00001457ul,
+};
+#endif
+
+#ifdef CONFIG_K2E_EVM
+/* DDR3 PHY configuration data with 1600M rate, and 4GB size  */
+struct ddr3_phy_config ddr3phy_1600_4g = {
+	.pllcr          = 0x0001C000ul,
+	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
+	.pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
+	.ptr0           = 0x42C21590ul,
+	.ptr1           = 0xD05612C0ul,
+	.ptr2           = 0, /* not set in gel */
+	.ptr3           = 0x08861A80ul,
+	.ptr4           = 0x0C827100ul,
+	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+	.dcr_val        = ((1 << 10)),
+	.dtpr0          = 0x9D9CBB66ul,
+	.dtpr1          = 0x12840300ul,
+	.dtpr2          = 0x5002D200ul,
+	.mr0            = 0x00001C70ul,
+	.mr1            = 0x00000006ul,
+	.mr2            = 0x00000018ul,
+	.dtcr           = 0x710035C7ul,
+	.pgcr2          = 0x00F07A12ul,
+	.zq0cr1         = 0x0001005Dul,
+	.zq1cr1         = 0x0001005Bul,
+	.zq2cr1         = 0x0001005Bul,
+	.pir_v1         = 0x00000033ul,
+	.pir_v2         = 0x0000FF81ul,
+};
+
+/* DDR3 EMIF configuration data with 1600M rate, and 4GB size  */
+struct ddr3_emif_config ddr3_1600_4g = {
+	.sdcfg          = 0x6200CE62ul,
+	.sdtim1         = 0x166C9855ul,
+	.sdtim2         = 0x00001D4Aul,
+	.sdtim3         = 0x421DFF53ul,
+	.sdtim4         = 0x543F07FFul,
+	.zqcfg          = 0x70073200ul,
+	.sdrfc          = 0x00001869ul,
+};
+#endif
+
+int ddr3_get_dimm_params(char *dimm_name)
+{
+	int ret;
+	int old_bus;
+	u8 spd_params[256];
+
+	i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
+
+	old_bus = i2c_get_bus_num();
+	i2c_set_bus_num(1);
+
+	ret = i2c_read(0x53, 0, 1, spd_params, 256);
+
+	i2c_set_bus_num(old_bus);
+
+	dimm_name[0] = '\0';
+
+	if (ret) {
+		puts("Cannot read DIMM params\n");
+		return 1;
+	}
+
+	/*
+	 * We need to convert spd data to dimm parameters
+	 * and to DDR3 EMIF and PHY regirsters values.
+	 * For now we just return DIMM type string value.
+	 * Caller may use this value to choose appropriate
+	 * a pre-set DDR3 configuration
+	 */
+
+	strncpy(dimm_name, (char *)&spd_params[0x80], 18);
+	dimm_name[18] = '\0';
+
+	return 0;
+}
diff --git a/board/ti/ks2_evm/ddr3_cfg.h b/board/ti/ks2_evm/ddr3_cfg.h
new file mode 100644
index 0000000000..15fcf52ef1
--- /dev/null
+++ b/board/ti/ks2_evm/ddr3_cfg.h
@@ -0,0 +1,24 @@
+/*
+ * Keystone2: DDR3 configuration
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __DDR3_CFG_H
+#define __DDR3_CFG_H
+
+extern struct ddr3_phy_config ddr3phy_1600_8g;
+extern struct ddr3_emif_config ddr3_1600_8g;
+
+extern struct ddr3_phy_config ddr3phy_1333_2g;
+extern struct ddr3_emif_config ddr3_1333_2g;
+
+extern struct ddr3_phy_config ddr3phy_1600_4g;
+extern struct ddr3_emif_config ddr3_1600_4g;
+
+int ddr3_get_dimm_params(char *dimm_name);
+
+#endif /* __DDR3_CFG_H */
diff --git a/board/ti/ks2_evm/ddr3_k2e.c b/board/ti/ks2_evm/ddr3_k2e.c
new file mode 100644
index 0000000000..40fd96607d
--- /dev/null
+++ b/board/ti/ks2_evm/ddr3_k2e.c
@@ -0,0 +1,55 @@
+/*
+ * Keystone2: DDR3 initialization
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include "ddr3_cfg.h"
+#include <asm/arch/ddr3.h>
+
+static int ddr3_size;
+static struct pll_init_data ddr3_400 = DDR3_PLL_400;
+
+void ddr3_init(void)
+{
+	char dimm_name[32];
+
+	if (~(readl(KS2_PLL_CNTRL_BASE + KS2_RSTCTRL_RSTYPE) & 0x1))
+		init_pll(&ddr3_400);
+
+	ddr3_get_dimm_params(dimm_name);
+
+	printf("Detected SO-DIMM [%s]\n", dimm_name);
+
+	/* Reset DDR3 PHY after PLL enabled */
+	ddr3_reset_ddrphy();
+
+	if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
+		/* 8G SO-DIMM */
+		ddr3_size = 8;
+		printf("DRAM: 8 GiB\n");
+		ddr3phy_1600_8g.zq0cr1 |= 0x10000;
+		ddr3phy_1600_8g.zq1cr1 |= 0x10000;
+		ddr3phy_1600_8g.zq2cr1 |= 0x10000;
+		ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
+		ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_8g);
+	} else if (!strcmp(dimm_name, "18KSF51272HZ-1G6K2")) {
+		/* 4G SO-DIMM */
+		ddr3_size = 4;
+		printf("DRAM: 4 GiB\n");
+		ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_4g);
+		ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_4g);
+	}
+}
+
+/**
+ * ddr3_get_size - return ddr3 size in GiB
+ */
+int ddr3_get_size(void)
+{
+	return ddr3_size;
+}
diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c
new file mode 100644
index 0000000000..21a5a0a252
--- /dev/null
+++ b/board/ti/ks2_evm/ddr3_k2hk.c
@@ -0,0 +1,84 @@
+/*
+ * Keystone2: DDR3 initialization
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include "ddr3_cfg.h"
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+
+struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
+struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
+
+void ddr3_init(void)
+{
+	char dimm_name[32];
+
+	ddr3_get_dimm_params(dimm_name);
+
+	printf("Detected SO-DIMM [%s]\n", dimm_name);
+
+	if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
+		init_pll(&ddr3a_400);
+		if (cpu_revision() > 0) {
+			if (cpu_revision() > 1) {
+				/* PG 2.0 */
+				/* Reset DDR3A PHY after PLL enabled */
+				ddr3_reset_ddrphy();
+				ddr3phy_1600_8g.zq0cr1 |= 0x10000;
+				ddr3phy_1600_8g.zq1cr1 |= 0x10000;
+				ddr3phy_1600_8g.zq2cr1 |= 0x10000;
+				ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
+						 &ddr3phy_1600_8g);
+			} else {
+				/* PG 1.1 */
+				ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
+						 &ddr3phy_1600_8g);
+			}
+
+			ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
+					  &ddr3_1600_8g);
+			printf("DRAM:  Capacity 8 GiB (includes reported below)\n");
+		} else {
+			ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
+			ddr3_1600_8g.sdcfg |= 0x1000;
+			ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
+					  &ddr3_1600_8g);
+			printf("DRAM:  Capacity 4 GiB (includes reported below)\n");
+		}
+	} else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
+		init_pll(&ddr3a_333);
+		if (cpu_revision() > 0) {
+			if (cpu_revision() > 1) {
+				/* PG 2.0 */
+				/* Reset DDR3A PHY after PLL enabled */
+				ddr3_reset_ddrphy();
+				ddr3phy_1333_2g.zq0cr1 |= 0x10000;
+				ddr3phy_1333_2g.zq1cr1 |= 0x10000;
+				ddr3phy_1333_2g.zq2cr1 |= 0x10000;
+				ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
+						 &ddr3phy_1333_2g);
+			} else {
+				/* PG 1.1 */
+				ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
+						 &ddr3phy_1333_2g);
+			}
+			ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
+					  &ddr3_1333_2g);
+		} else {
+			ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g);
+			ddr3_1333_2g.sdcfg |= 0x1000;
+			ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
+					  &ddr3_1333_2g);
+		}
+	} else {
+		printf("Unknown SO-DIMM. Cannot configure DDR3\n");
+		while (1)
+			;
+	}
+}