arm: imx6: tqma6: add support for TQMa6DL variant

This adds support for TQMa6DL using i.MX6DL and 1GiB DRAM
Since The module will use the same devicetree, we patch
the ram size in ft_board_setup.

Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>

5 files changed, 145 insertions, 2 deletions

diff --git a/board/tqc/tqma6/Kconfig b/board/tqc/tqma6/Kconfig
index 5dafa3822a..6df4134286 100644
--- a/board/tqc/tqma6/Kconfig
+++ b/board/tqc/tqma6/Kconfig
@@ -22,6 +22,12 @@ config TQMA6Q
 	help
 	  select TQMa6Q / TQMa6D with i.MX6Q/D and 1GiB DRAM
 
+config TQMA6DL
+	bool "TQMa6DL"
+	select MX6DL
+	help
+	  select TQMa6DL with i.MX6DL and 1GiB DRAM
+
 config TQMA6S
 	bool "TQMa6S"
 	select MX6S
@@ -70,6 +76,7 @@ endchoice
 
 config IMX_CONFIG
 	default "board/tqc/tqma6/tqma6q.cfg" if TQMA6Q
+	default "board/tqc/tqma6/tqma6dl.cfg" if TQMA6DL
 	default "board/tqc/tqma6/tqma6s.cfg" if TQMA6S
 
 endif
diff --git a/board/tqc/tqma6/README b/board/tqc/tqma6/README
index 2c012e7b75..c47cb21eeb 100644
--- a/board/tqc/tqma6/README
+++ b/board/tqc/tqma6/README
@@ -21,6 +21,7 @@ To build U-Boot for the TQ Systems TQMa6 modules:
 
 x is a placeholder for the CPU variant
 q - means i.MX6Q/D: TQMa6Q (i.MX6Q) and TQMa6D  (i.MX6D)
+dl - means i.MX6DL: TQMa6DL  (i.MX6DL)
 s - means i.MX6S: TQMa6S  (i.MX6S)
 
 baseboard is a placeholder for the boot device
@@ -31,5 +32,7 @@ This gives the following configurations:
 
 tqma6q_mba6_mmc_config
 tqma6q_mba6_spi_config
+tqma6dl_mba6_mmc_config
+tqma6dl_mba6_spi_config
 tqma6s_mba6_mmc_config
 tqma6s_mba6_spi_config
diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c
index 49917c1d64..fdb0fa11b0 100644
--- a/board/tqc/tqma6/tqma6.c
+++ b/board/tqc/tqma6/tqma6.c
@@ -269,8 +269,15 @@ int checkboard(void)
  * Device Tree Support
  */
 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+#define MODELSTRLEN 32u
 int ft_board_setup(void *blob, bd_t *bd)
 {
+	char modelstr[MODELSTRLEN];
+
+	snprintf(modelstr, MODELSTRLEN, "TQ %s on %s", tqma6_get_boardname(),
+		 tqma6_bb_get_boardname());
+	do_fixup_by_path_string(blob, "/", "model", modelstr);
+	fdt_fixup_memory(blob, (u64)PHYS_SDRAM, (u64)gd->ram_size);
 	/* bring in eMMC dsr settings */
 	do_fixup_by_path_u32(blob,
 			     "/soc/aips-bus@02100000/usdhc@02198000",
diff --git a/board/tqc/tqma6/tqma6_mba6.c b/board/tqc/tqma6/tqma6_mba6.c
index 0be7845cc3..43349ade1d 100644
--- a/board/tqc/tqma6/tqma6_mba6.c
+++ b/board/tqc/tqma6/tqma6_mba6.c
@@ -59,7 +59,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII	0x02e0790
 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM	0x02e07ac
 
-#elif defined(CONFIG_TQMA6S)
+#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
 
 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII	0x02e0768
 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM	0x02e0788
@@ -245,13 +245,14 @@ int board_phy_config(struct phy_device *phydev)
  * optimized pad skew values depends on CPU variant on the TQMa6x module:
  * CONFIG_TQMA6Q: i.MX6Q/D
  * CONFIG_TQMA6S: i.MX6S
+ * CONFIG_TQMA6DL: i.MX6DL
  */
 #if defined(CONFIG_TQMA6Q)
 #define MBA6X_KSZ9031_CTRL_SKEW	0x0032
 #define MBA6X_KSZ9031_CLK_SKEW	0x03ff
 #define MBA6X_KSZ9031_RX_SKEW	0x3333
 #define MBA6X_KSZ9031_TX_SKEW	0x2036
-#elif defined(CONFIG_TQMA6S)
+#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
 #define MBA6X_KSZ9031_CTRL_SKEW	0x0030
 #define MBA6X_KSZ9031_CLK_SKEW	0x03ff
 #define MBA6X_KSZ9031_RX_SKEW	0x3333
diff --git a/board/tqc/tqma6/tqma6dl.cfg b/board/tqc/tqma6/tqma6dl.cfg
new file mode 100644
index 0000000000..716033f3fb
--- /dev/null
+++ b/board/tqc/tqma6/tqma6dl.cfg
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2014 - 2015 Markus Niebel <Markus.Niebel@tq-group.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+#if defined(CONFIG_TQMA6X_MMC_BOOT)
+BOOT_FROM      sd
+#elif defined(CONFIG_TQMA6X_SPI_BOOT)
+BOOT_FROM      spi
+#endif
+
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* TQMa6DL DDR config Rev. 0100E */
+/* IOMUX configuration */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030
+DATA 4, MX6_IOM_DRAM_CAS, 0x00008030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00008030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030
+
+/* memory interface calibration values */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00440048
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x003D003F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0029002D
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x002B0043
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x424C0250
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02300234
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4234023C
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0224022C
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x48484C4C
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4C4E4E4C
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x36382C36
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x34343630
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+
+/* configure memory interface */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x3F435333
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8B63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
+DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00408032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022222
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002552D
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+
+#include "clocks.cfg"