diff options
| author | wdenk <wdenk> | 2004-07-11 17:40:54 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2004-07-11 17:40:54 +0000 |
| commit | 56523f12830227fc18437bf935fefdb10fe25cca (patch) | |
| tree | 11ad0e08e2284224ebde36161e184450510b9f03 /board/tqm5200/mt48lc16m16a2-75.h | |
| parent | 857cad37a41c431582a74be56f858ee0476cd0d9 (diff) | |
* Patch by Martin Krause, 30 Jun 2004:
Add support for TQM5200 board
* Patch by Martin Krause, 29 Jun 2004:
Add loopw command: infinite write loop on address range
Diffstat (limited to 'board/tqm5200/mt48lc16m16a2-75.h')
| -rw-r--r-- | board/tqm5200/mt48lc16m16a2-75.h | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/board/tqm5200/mt48lc16m16a2-75.h b/board/tqm5200/mt48lc16m16a2-75.h new file mode 100644 index 0000000000..3f1e1691bb --- /dev/null +++ b/board/tqm5200/mt48lc16m16a2-75.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 0 /* is SDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x00CD0000 +/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */ +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xD2322800 +/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */ +/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */ +#define SDRAM_CONFIG2 0x8AD70000 +/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */ + +#elif defined(CONFIG_MGT5100) +/* Settings for XLB = 66 MHz */ +#define SDRAM_MODE 0x008D0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xC2222600 +#define SDRAM_CONFIG2 0x88B70004 +#define SDRAM_ADDRSEL 0x02000000 + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif |