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| author | Wolfgang Denk <wd@atlas.denx.de> | 2006-06-19 01:37:03 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@atlas.denx.de> | 2006-06-19 01:37:03 +0200 |
| commit | a650cfa286e8933144a776693d56dfd858922aa4 (patch) | |
| tree | 1848c6ba3c8115b516d6711cad787d1e6a9d2fb5 /board/tqm834x/tqm834x.c | |
| parent | df02bd1b3f2eecca04bfecb62eae7c2ff698506a (diff) | |
| parent | 0c32d96ddd7309b86ff92dfc1f3694908f174cf6 (diff) | |
Merge with ssh://fifi/home/wd/git/u-boot/master
Diffstat (limited to 'board/tqm834x/tqm834x.c')
| -rw-r--r-- | board/tqm834x/tqm834x.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c index b5c12e3e24..d992aec381 100644 --- a/board/tqm834x/tqm834x.c +++ b/board/tqm834x/tqm834x.c @@ -406,4 +406,28 @@ static void set_ddr_config(void) { (DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) | (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT); SYNC; + + /* Workaround for DDR6 Erratum + * see MPC8349E Device Errata Rev.8, 2/2006 + * This workaround influences the MPC internal "input enables" + * dependent on CAS latency and MPC revision. According to errata + * sheet the internal reserved registers for this workaround are + * not available from revision 2.0 and up. + */ + + /* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0 + * (0x200) + */ + if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) { + + /* There is a internal reserved register at IMMRBAR+0x2F00 + * which has to be written with a certain value defined by + * errata sheet. + */ +#if defined(DDR_CASLAT_20) + *((u8 *)im + 0x2f00) = 0x201c0000; +#else + *((u8 *)im + 0x2f00) = 0x202c0000; +#endif + } } |