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author | Lukas Auer <lukas.auer@aisec.fraunhofer.de> | 2019-03-17 19:28:34 +0100 |
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committer | Andes <uboot@andestech.com> | 2019-04-08 09:44:26 +0800 |
commit | f152febb2a97696f7c7e6df46bf585cfc962a835 (patch) | |
tree | 50daf485b2c0e168be7b1b59cb150f58b40b89d1 /board/ve8313/MAINTAINERS | |
parent | 34a0626fc344f51cd768efecdd52628b677fb9a8 (diff) |
riscv: implement IPI platform functions using SBI
The supervisor binary interface (SBI) provides the necessary functions
to implement the platform IPI functions riscv_send_ipi() and
riscv_clear_ipi(). Use it to implement them.
This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs
running in supervisor mode. Support for machine mode is already
available for CPUs that include the SiFive CLINT.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'board/ve8313/MAINTAINERS')
0 files changed, 0 insertions, 0 deletions