diff options
| author | Stefan Roese <sr@denx.de> | 2009-09-24 13:59:57 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2009-09-28 10:45:54 +0200 |
| commit | 95b602bab5fec2fffab07a01ea3947c70d1bacc1 (patch) | |
| tree | acee523787d213090cc592029f1d566473bc1fd7 /board/w7o | |
| parent | 952e7760bfc5b0e3b142b9ce34e7fbb7d008c900 (diff) | |
ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper case
The latest PPC4xx register cleanup patch missed some SDRAM defines.
This patch now changes lower case UIC defines to upper case. Also
some names are changed to match the naming in the IBM/AMCC users
manuals (e.g. mem_mcopt1 -> SDRAM0_CFG).
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/w7o')
| -rw-r--r-- | board/w7o/init.S | 10 | ||||
| -rw-r--r-- | board/w7o/w7o.c | 8 |
2 files changed, 9 insertions, 9 deletions
diff --git a/board/w7o/init.S b/board/w7o/init.S index 090b07a1e6..5477f986b9 100644 --- a/board/w7o/init.S +++ b/board/w7o/init.S @@ -182,7 +182,7 @@ sdram_init: * Disable memory controller to allow * values to be changed. */ - addi r3, 0, mem_mcopt1 + addi r3, 0, SDRAM0_CFG mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x0 ori r4, r4, 0x0 @@ -192,7 +192,7 @@ sdram_init: * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2 * All other banks are disabled. */ - addi r3, 0, mem_mb0cf + addi r3, 0, SDRAM0_B0CR mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */ ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */ @@ -222,7 +222,7 @@ sdram_init: /* * Set up SDTR1 */ - addi r3, 0, mem_sdtr1 + addi r3, 0, SDRAM0_TR mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */ ori r4, r4, 0x400D @@ -231,7 +231,7 @@ sdram_init: /* * Set RTR */ - addi r3, 0, mem_rtr + addi r3, 0, SDRAM0_RTR mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms@100Mhz */ mtdcr SDRAM0_CFGDATA, r4 @@ -250,7 +250,7 @@ sdram_init: /******************************************************************** * Set memory controller options reg, MCOPT1. *******************************************************************/ - addi r3, 0, mem_mcopt1 + addi r3, 0, SDRAM0_CFG mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */ ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */ diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c index 00a9f98b44..a818808ba0 100644 --- a/board/w7o/w7o.c +++ b/board/w7o/w7o.c @@ -170,16 +170,16 @@ unsigned long get_dram_size (void) int size = 0; /* Get bank Size registers */ - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); /* get bank 0 config reg */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); /* get bank 0 config reg */ regs[0] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); /* get bank 1 config reg */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); /* get bank 1 config reg */ regs[1] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); /* get bank 2 config reg */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); /* get bank 2 config reg */ regs[2] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); /* get bank 3 config reg */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); /* get bank 3 config reg */ regs[3] = mfdcr (SDRAM0_CFGDATA); /* compute the size, add each bank if enabled */ |