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authorMichal Simek <monstr@monstr.eu>2007-09-24 00:08:37 +0200
committerMichal Simek <monstr@monstr.eu>2007-09-24 00:08:37 +0200
commitb90c045f035c3cc9b5d2edaed6048dfb74e40763 (patch)
treeee69b8872cf8c295a48244280c82d98e191111ab /board/xilinx/xupv2p/xparameters.h
parent6b6f287a33ae8c340f97fb08ed95b6687e2baa4b (diff)
synchronizition with mainline
Diffstat (limited to 'board/xilinx/xupv2p/xparameters.h')
-rw-r--r--board/xilinx/xupv2p/xparameters.h27
1 files changed, 12 insertions, 15 deletions
diff --git a/board/xilinx/xupv2p/xparameters.h b/board/xilinx/xupv2p/xparameters.h
index 0bb7a805f4..a96c693c55 100644
--- a/board/xilinx/xupv2p/xparameters.h
+++ b/board/xilinx/xupv2p/xparameters.h
@@ -28,24 +28,17 @@
/* System Clock Frequency */
#define XILINX_CLOCK_FREQ 100000000
-/* Microblaze is microblaze_0 */
-#define XILINX_USE_MSR_INSTR 1
-#define XILINX_PVR 0
-#define XILINX_FSL_NUMBER 0
-
/* Interrupt controller is opb_intc_0 */
#define XILINX_INTC_BASEADDR 0x41200000
-#define XILINX_INTC_NUM_INTR_INPUTS 7
+#define XILINX_INTC_NUM_INTR_INPUTS 11
/* Timer pheriphery is opb_timer_1 */
#define XILINX_TIMER_BASEADDR 0x41c00000
-#define XILINX_TIMER_IRQ 0
+#define XILINX_TIMER_IRQ 1
/* Uart pheriphery is RS232_Uart_1 */
-#define XILINX_UARTLITE_BASEADDR 0x40600000
-#define XILINX_UARTLITE_BAUDRATE 115200
-
-/* IIC doesn't exist */
+#define XILINX_UART_BASEADDR 0x40600000
+#define XILINX_UART_BAUDRATE 115200
/* GPIO is LEDs_4Bit*/
#define XILINX_GPIO_BASEADDR 0x40000000
@@ -58,10 +51,14 @@
/* Sysace Controller is SysACE_CompactFlash */
#define XILINX_SYSACE_BASEADDR 0x41800000
+#define XILINX_SYSACE_HIGHADDR 0x4180ffff
#define XILINX_SYSACE_MEM_WIDTH 16
/* Ethernet controller is Ethernet_MAC */
-#define XILINX_EMAC_BASEADDR 0x40c00000
-#define XILINX_EMAC_DMA_PRESENT 3
-#define XILINX_EMAC_HALF_DUPLEX_EXIST 1
-#define XILINX_EMAC_MII_EXIST 1
+#define XPAR_XEMAC_NUM_INSTANCES 1
+#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
+#define XPAR_OPB_ETHERNET_0_BASEADDR 0x40c00000
+#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0ffff
+#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
+#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
+#define XPAR_OPB_ETHERNET_0_MII_EXIST 1