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| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-05-23 22:50:23 +0200 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-05-23 22:50:23 +0200 |
| commit | c534d2fdcf7aa80230a0f1ed54d5e3164ba595eb (patch) | |
| tree | 7c00728aa9d0c4cecf2d9203eebc093dbebbc07a /board/xilinx/zynq/board.c | |
| parent | 10dc77716f41979e03baf3b847b97dc7279ef30d (diff) | |
| parent | 9f9d41bad16efe0674257b4efe4db1a399f93643 (diff) | |
Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master'
Diffstat (limited to 'board/xilinx/zynq/board.c')
| -rw-r--r-- | board/xilinx/zynq/board.c | 25 |
1 files changed, 15 insertions, 10 deletions
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index c8cc2bc934..258632e52b 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -6,6 +6,8 @@ #include <common.h> #include <fdtdec.h> +#include <fpga.h> +#include <mmc.h> #include <netdev.h> #include <zynqpl.h> #include <asm/arch/hardware.h> @@ -13,21 +15,23 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_FPGA -xilinx_desc fpga; +#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static xilinx_desc fpga; /* It can be done differently */ -xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); -xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); -xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); -xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); -xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); -xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); +static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); +static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); +static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); +static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); +static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); +static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); #endif int board_init(void) { -#ifdef CONFIG_FPGA +#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) u32 idcode; idcode = zynq_slcr_get_idcode(); @@ -54,7 +58,8 @@ int board_init(void) } #endif -#ifdef CONFIG_FPGA +#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) fpga_init(); fpga_add(fpga_xilinx, &fpga); #endif |