arm: zynq: Convert all board to use arch ps7_init code

Use generic implementation. It will also reduce config data size for
converted boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

2 files changed, 1 insertions, 274 deletions

diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
index ed7c2a64e1..84625f0746 100644
--- a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include "ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
 
 unsigned long ps7_pll_init_data_3_0[] = {
 	/* START: top */
@@ -12666,145 +12666,6 @@ unsigned long ps7_post_config_1_0[] = {
 
 
 #include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char *getPS7MessageInfo(unsigned key)
-{
-	char *err_msg = "";
-	switch (key) {
-	case PS7_INIT_SUCCESS:
-		err_msg = "PS7 initialization successful";
-		break;
-	case PS7_INIT_CORRUPT:
-		err_msg = "PS7 init Data Corrupted";
-		break;
-	case PS7_INIT_TIMEOUT:
-		err_msg = "PS7 init mask poll timeout";
-		break;
-	case PS7_POLL_FAILED_DDR_INIT:
-		err_msg = "Mask Poll failed for DDR Init";
-		break;
-	case PS7_POLL_FAILED_DMA:
-		err_msg = "Mask Poll failed for PLL Init";
-		break;
-	case PS7_POLL_FAILED_PLL:
-		err_msg = "Mask Poll failed for DMA done bit";
-		break;
-	default:
-		err_msg = "Undefined error status";
-		break;
-	}
-
-	return err_msg;
-}
-
-unsigned long ps7GetSiliconVersion(void)
-{
-	/* Read PS version from MCTRL register [31:28] */
-	unsigned long mask = 0xF0000000;
-	unsigned long *addr = (unsigned long *)0XF8007080;
-	unsigned long ps_version = (*addr & mask) >> 28;
-	return ps_version;
-}
-
-void mask_write(unsigned long add, unsigned long mask, unsigned long val)
-{
-	unsigned long *addr = (unsigned long *)add;
-	*addr = (val & mask) | (*addr & ~mask);
-}
-
-int mask_poll(unsigned long add, unsigned long mask)
-{
-	volatile unsigned long *addr = (volatile unsigned long *)add;
-	int i = 0;
-	while (!(*addr & mask)) {
-		if (i == PS7_MASK_POLL_TIME)
-			return -1;
-		i++;
-	}
-	return 1;
-}
-
-unsigned long mask_read(unsigned long add, unsigned long mask)
-{
-	unsigned long *addr = (unsigned long *)add;
-	unsigned long val = (*addr & mask);
-	return val;
-}
-
-int ps7_config(unsigned long *ps7_config_init)
-{
-	unsigned long *ptr = ps7_config_init;
-
-	unsigned long opcode;	/* current instruction .. */
-	unsigned long args[16];	/* no opcode has so many args ... */
-	int numargs;		/* number of arguments of this instruction */
-	int j;			/* general purpose index */
-
-	volatile unsigned long *addr;	/* some variable to make code readable */
-	unsigned long val, mask;	/* some variable to make code readable */
-
-	int finish = -1;	/* loop while this is negative ! */
-	int i = 0;		/* Timeout variable */
-
-	while (finish < 0) {
-		numargs = ptr[0] & 0xF;
-		opcode = ptr[0] >> 4;
-
-		for (j = 0; j < numargs; j++)
-			args[j] = ptr[j + 1];
-		ptr += numargs + 1;
-
-		switch (opcode) {
-		case OPCODE_EXIT:
-			finish = PS7_INIT_SUCCESS;
-			break;
-
-		case OPCODE_CLEAR:
-			addr = (unsigned long *)args[0];
-			*addr = 0;
-			break;
-
-		case OPCODE_WRITE:
-			addr = (unsigned long *)args[0];
-			val = args[1];
-			*addr = val;
-			break;
-
-		case OPCODE_MASKWRITE:
-			addr = (unsigned long *)args[0];
-			mask = args[1];
-			val = args[2];
-			*addr = (val & mask) | (*addr & ~mask);
-			break;
-
-		case OPCODE_MASKPOLL:
-			addr = (unsigned long *)args[0];
-			mask = args[1];
-			i = 0;
-			while (!(*addr & mask)) {
-				if (i == PS7_MASK_POLL_TIME) {
-					finish = PS7_INIT_TIMEOUT;
-					break;
-				}
-				i++;
-			}
-			break;
-		case OPCODE_MASKDELAY:
-			addr = (unsigned long *)args[0];
-			mask = args[1];
-			int delay = get_number_of_cycles_for_delay(mask);
-			perf_reset_and_start_timer();
-			while ((*addr < delay))
-				;
-			break;
-		default:
-			finish = PS7_INIT_CORRUPT;
-			break;
-		}
-	}
-	return finish;
-}
 
 unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
 unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
@@ -12892,40 +12753,3 @@ int ps7_init(void)
 	return PS7_INIT_SUCCESS;
 }
 
-/* For delay calculation using global timer */
-
-/* start timer */
-void perf_start_clock(void)
-{
-	*(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) |	/* Timer Enable */
-							      (1 << 3) |	/* Auto-increment */
-							      (0 << 8)	/* Pre-scale */
-	    );
-}
-
-/* stop timer and reset timer count regs */
-void perf_reset_clock(void)
-{
-	perf_disable_clock();
-	*(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
-	*(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
-	/* GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) */
-	return APU_FREQ * delay / (2 * 1000);
-}
-
-/* stop timer */
-void perf_disable_clock(void)
-{
-	*(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer(void)
-{
-	perf_reset_clock();
-	perf_start_clock();
-}
diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h
deleted file mode 100644
index 929251afc5..0000000000
--- a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Copyright (c) Xilinx, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*typedef unsigned int  u32; */
-
-/** do we need to make this name more unique ? **/
-/*extern u32 ps7_init_data[]; */
-extern unsigned long *ps7_ddr_init_data;
-extern unsigned long *ps7_mio_init_data;
-extern unsigned long *ps7_pll_init_data;
-extern unsigned long *ps7_clock_init_data;
-extern unsigned long *ps7_peripherals_init_data;
-
-#define OPCODE_EXIT       0U
-#define OPCODE_CLEAR      1U
-#define OPCODE_WRITE      2U
-#define OPCODE_MASKWRITE  3U
-#define OPCODE_MASKPOLL   4U
-#define OPCODE_MASKDELAY  5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT()                   ((OPCODE_EXIT      << 4) | 0)
-#define EMIT_CLEAR(addr)              ((OPCODE_CLEAR     << 4) | 1) , addr
-#define EMIT_WRITE(addr, val)          ((OPCODE_WRITE     << 4) | 2) , addr, val
-#define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) , addr, mask, val
-#define EMIT_MASKPOLL(addr, mask)      ((OPCODE_MASKPOLL  << 4) | 2) , addr, mask
-#define EMIT_MASKDELAY(addr, mask)      ((OPCODE_MASKDELAY << 4) | 2) , addr, mask
-
-/* Returns codes  of PS7_Init */
-#define PS7_INIT_SUCCESS   (0)	/* 0 is success in good old C */
-#define PS7_INIT_CORRUPT   (1)	/* 1 the data is corrupted, and slcr reg are in corrupted state now */
-#define PS7_INIT_TIMEOUT   (2)	/* 2 when a poll operation timed out */
-#define PS7_POLL_FAILED_DDR_INIT (3)	/* 3 when a poll operation timed out for ddr init */
-#define PS7_POLL_FAILED_DMA      (4)	/* 4 when a poll operation timed out for dma done bit */
-#define PS7_POLL_FAILED_PLL      (5)	/* 5 when a poll operation timed out for pll sequence init */
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ  650000000
-#define DDR_FREQ  525000000
-#define DCI_FREQ  10096154
-#define QSPI_FREQ  200000000
-#define SMC_FREQ  10000000
-#define ENET0_FREQ  125000000
-#define ENET1_FREQ  10000000
-#define USB0_FREQ  60000000
-#define USB1_FREQ  60000000
-#define SDIO_FREQ  50000000
-#define UART_FREQ  100000000
-#define SPI_FREQ  10000000
-#define I2C_FREQ  108333336
-#define WDT_FREQ  108333336
-#define TTC_FREQ  50000000
-#define CAN_FREQ  10000000
-#define PCAP_FREQ  200000000
-#define TPIU_FREQ  200000000
-#define FPGA0_FREQ  100000000
-#define FPGA1_FREQ  142857132
-#define FPGA2_FREQ  200000000
-#define FPGA3_FREQ  50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
-
-int ps7_config(unsigned long *);
-int ps7_init(void);
-int ps7_post_config(void);
-char *getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer(void);
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif